Cortex-M0+ Devices Generic User Guide - Keil

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The Cortex-M0+ Instruction Set3.6.1 B, BL, BX, and BLXBranch instructions.SyntaxB{cond} labelBL labelBX RmBLX Rmwhere:cond Is an optional condition code, see Conditional execution on page 3-9.label Is a PC-relative expression. See PC-relative expressions on page 3-9.Rm Is a register providing the address to branch to.OperationAll these instructions cause a branch to the address indicated by label or contained in theregister specified by Rm. In addition:• the BL and BLX instructions write the address of the next instruction to LR, the link registerR14.• the BX and BLX instructions result in a HardFault exception if bit[0] of Rm is 0.BL and BLX instructions also set bit[0] of the LR to 1. This ensures that the value is suitable foruse by a subsequent POP {PC} or BX instruction to perform a successful return branch.Table 3-9 shows the ranges for the various branch instructions.Table 3-9 Branch rangesInstructionB labelBcond labelBL labelBX RmBLX RmBranch range−2 KB to +2 KB−256 bytes to +254 bytes−16 MB to +16 MBAny value in registerAny value in registerRestrictionsIn these instructions:• Do not use SP or PC in the BX or BLX instruction.• For BX and BLX, bit[0] of Rm must be 1 for correct execution. Bit[0] is used to update theEPSR T-bit and is discarded from the target address.NoteBcond is the only conditional instruction on the Cortex-M0+ processor.ARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 3-34ID041812Non-Confidential
The Cortex-M0+ Instruction SetCondition flagsThese instructions do not change the flags.ExamplesB loopA ; Branch to loopABL funC ; Branch with link (Call) to function funC, return address; stored in LRBX LR ; Return from function callBLX R0 ; Branch with link and exchange (Call) to a address stored; in R0BEQ labelD ; Conditionally branch to labelD if last flag setting; instruction set the Z flag, else do not branch.ARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 3-35ID041812Non-Confidential
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Cortex-M0+ DevicesGeneric User Guid
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ContentsCortex-M0+ Devices Generic
Page 7 and 8:
PrefaceTypographical ConventionsThe
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Chapter 1IntroductionThis chapter i
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IntroductionThe tight integration o
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Chapter 2The Cortex-M0+ ProcessorTh
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The Cortex-M0+ ProcessorIn Thread m
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The Cortex-M0+ ProcessorAccess thes
Page 19 and 20: The Cortex-M0+ ProcessorInterruptib
Page 21 and 22: The Cortex-M0+ Processor2.1.5 Data
Page 23 and 24: The Cortex-M0+ ProcessorThe differe
Page 25 and 26: The Cortex-M0+ ProcessorTable 2-10
Page 27 and 28: The Cortex-M0+ ProcessorLittle-endi
Page 29 and 30: The Cortex-M0+ ProcessorSysTickInte
Page 31 and 32: The Cortex-M0+ ProcessorIf software
Page 33 and 34: The Cortex-M0+ ProcessorThe process
Page 35 and 36: The Cortex-M0+ Processor2.5 Power m
Page 37 and 38: Chapter 3The Cortex-M0+ Instruction
Page 39 and 40: The Cortex-M0+ Instruction SetTable
Page 41 and 42: The Cortex-M0+ Instruction Set3.2 I
Page 43 and 44: The Cortex-M0+ Instruction SetNote
Page 45 and 46: The Cortex-M0+ Instruction Set3.3.5
Page 47 and 48: The Cortex-M0+ Instruction Set3.4 M
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Page 61 and 62: The Cortex-M0+ Instruction SetExamp
Page 69: The Cortex-M0+ Instruction Set3.6 B
Page 85 and 86: Chapter 4Cortex-M0+ PeripheralsThe
Page 87 and 88: Cortex-M0+ Peripherals4.2 Nested Ve
Page 89 and 90: Cortex-M0+ PeripheralsThe bit assig
Page 91 and 92: Cortex-M0+ Peripherals4.2.7 NVIC us
Page 93 and 94: Cortex-M0+ PeripheralsBits Name Fun
Page 95 and 96: Cortex-M0+ PeripheralsTable 4-11 IC
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Page 99 and 100: Cortex-M0+ PeripheralsSystem Handle
Page 101 and 102: Cortex-M0+ PeripheralsTable 4-20 SY
Page 103 and 104: Cortex-M0+ Peripherals4.5 Memory Pr
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Page 107 and 108: Cortex-M0+ PeripheralsTable 4-29 MP
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