Cortex-M0+ Devices Generic User Guide - Keil

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Cortex-M0+ PeripheralsTable 4-33 AP encoding (continued)AP[2:0]PrivilegedpermissionsUnprivilegedpermissionsDescription100 Unpredictable Unpredictable Reserved101 RO No access Reads by privileged software only110 RO RO Read only, by privileged or unprivileged software111 RO RO Read only, by privileged or unprivileged software4.5.7 MPU access permission faultsWhen an access violates the MPU permissions, the processor generates a HardFault.4.5.8 Updating an MPU regionTo update the attributes for an MPU region, update the MPU_RNR, MPU_RBAR andMPU_RASR registers.Updating an MPU regionSimple code to configure one region:; R1 = region number; R2 = size/enable; R3 = attributes; R4 = addressLDR R0,=MPU_RNRSTR R1, [R0, #0x0]STR R4, [R0, #0x4]STRH R2, [R0, #0x8]STRH R3, [R0, #0xA]; 0xE000ED98, MPU region number register; Region Number; Region Base Address; Region Size and Enable; Region AttributeSoftware must use memory barrier instructions:• before MPU setup if there might be outstanding memory transfers, such as bufferedwrites, that might be affected by the change in MPU settings• after MPU setup, if the software includes memory transfers that must use the new MPUsettings.However, an instruction synchronization barrier instruction is not required if the MPU setupprocess starts by entering an exception handler, or is followed by an exception return, becausethe exception entry and exception return mechanisms cause memory barrier behavior.For example, if you want all of the memory access behavior to take effect immediately after theprogramming sequence, use a DSB instruction and an ISB instruction. A DSB is required afterchanging MPU settings, such as at the end of context switch. An ISB is required if the code thatprograms the MPU region or regions is entered using a branch or call. If the programmingsequence is entered using a return from exception, or by taking an exception, then you do notrequire an ISB.SubregionsRegions are divided into eight equal-sized subregions. Set the corresponding bit in the SRDfield of the MPU_RASR to disable a subregion, see MPU Region Attribute and Size Register onpage 4-23. The least significant bit of SRD controls the first subregion, and the most significantARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 4-26ID041812Non-Confidential
Cortex-M0+ Peripheralsbit controls the last subregion. Disabling a subregion means another region overlapping thedisabled range matches instead. If no other enabled region overlaps the disabled subregion theMPU issues a fault.Example of SRD useTwo regions with the same base address overlap. Region one is 128KB, and region two is512KB. To ensure the attributes from region one apply to the first 128KB region, set the SRDfield for region two to b00000011 to disable the first two subregions, as the figure shows.Region 2, with Offset fromsubregions base address512KBBase address of both regionsRegion 1Disabled subregionDisabled subregion448KB384KB320KB256KB192KB128KB64KB04.5.9 MPU usage hints and tipsTo avoid unexpected behavior, disable the interrupts before updating the attributes of a regionthat the interrupt handlers might access.Ensure software uses aligned accesses of the correct size to access MPU registers, except for theMPU_RASR, it must use aligned word accesses to MPU registers.When setting up the MPU, and if the MPU has previously been programmed, disable unusedregions to prevent any previous region settings from affecting the new MPU setup.MPU configuration for a microcontrollerUsually, a microcontroller system has only a single processor and no caches. In such a system,program the MPU as follows:Table 4-34 Example memory region attributes for a microcontrollerMemory region C B S Memory type and attributesFlash memory 1 0 0 Normal memory, Non-shareable, write-throughInternal SRAM 1 0 1 Normal memory, Shareable, write-throughExternal SRAM 1 1 1 Normal memory, Shareable, write-back, write-allocatePeripherals 0 1 1 Device memory, ShareableIn most microcontroller implementations, the shareability and cache policy attributes do notaffect the system behavior. However, using these settings for the MPU regions can make theapplication code more portable. The values given are for typical situations. In special systems,such as multiprocessor designs or designs with a separate DMA engine, the shareability attributemight be important. In these cases see the recommendations of the memory devicemanufacturer.ARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 4-27ID041812Non-Confidential
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Cortex-M0+ DevicesGeneric User Guid
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ContentsCortex-M0+ Devices Generic
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PrefaceTypographical ConventionsThe
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Chapter 1IntroductionThis chapter i
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IntroductionThe tight integration o
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Chapter 2The Cortex-M0+ ProcessorTh
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The Cortex-M0+ ProcessorIn Thread m
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The Cortex-M0+ ProcessorAccess thes
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The Cortex-M0+ ProcessorInterruptib
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The Cortex-M0+ Processor2.1.5 Data
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The Cortex-M0+ ProcessorThe differe
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The Cortex-M0+ ProcessorTable 2-10
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The Cortex-M0+ ProcessorLittle-endi
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The Cortex-M0+ ProcessorSysTickInte
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The Cortex-M0+ ProcessorIf software
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The Cortex-M0+ ProcessorThe process
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The Cortex-M0+ Processor2.5 Power m
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Chapter 3The Cortex-M0+ Instruction
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The Cortex-M0+ Instruction SetTable
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The Cortex-M0+ Instruction Set3.2 I
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The Cortex-M0+ Instruction SetNote
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The Cortex-M0+ Instruction Set3.3.5
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The Cortex-M0+ Instruction Set3.4 M
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Cortex-M0+ Devices Generic User Guide - Keil

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