Cortex-M0+ Devices Generic User Guide - Keil

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The Cortex-M0+ ProcessorCONTROL registerThe CONTROL register controls the stack used, and the optional privilege level for softwareexecution, when the processor is in Thread mode. See the register summary in Table 2-2 onpage 2-3 for its attributes. The bit assignments are:31 2 1 0ReservedSPSELnPRIVBits Name Function[31:2] - ReservedTable 2-8 CONTROL register bit assignments[1] SPSEL Defines the current stack:0 = MSP is the current stack pointer1 = PSP is the current stack pointer.In Handler mode this bit reads as zero and ignores writes.[0] nPRIV aDefines the Thread mode privilege level:0 = Privileged1 = Unprivileged.a. If the Unprivileged/Privileged extension is not configured, this bit isReserved, RAZ.Handler mode always uses the MSP, so the processor ignores explicit writes to the active stackpointer bit of the CONTROL register when in Handler mode. The exception entry and returnmechanisms automatically update the CONTROL register.In an OS environment, ARM recommends that threads running in Thread mode use the processstack and the kernel and exception handlers use the main stack.By default, Thread mode uses the MSP. To switch the stack pointer used in Thread mode to thePSP, use the MSR instruction to set the Active stack pointer bit to 1, see MRS on page 3-42.NoteWhen changing the stack pointer, software must use an ISB instruction immediately after the MSRinstruction. This ensures that instructions after the ISB execute using the new stack pointer. SeeISB on page 3-41.2.1.4 Exceptions and interruptsThe Cortex-M0+ processor supports interrupts and system exceptions. The processor and theNested Vectored Interrupt Controller (NVIC) prioritize and handle all exceptions. An interruptor exception changes the normal flow of software control. The processor uses handler mode tohandle all exceptions except for reset. See Exception entry on page 2-20 and Exception returnon page 2-20 for more information.The NVIC registers control interrupt handling. See Nested Vectored Interrupt Controller onpage 4-3 for more information.ARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 2-8ID041812Non-Confidential
The Cortex-M0+ Processor2.1.5 Data typesThe processor:• Supports the following data types:— 32-bit words— 16-bit halfwords— 8-bit bytes.• Manages all data memory accesses as either little-endian or big-endian, depending on thedevice implementation. Instruction memory and Private Peripheral Bus (PPB) accessesare always little-endian. See Memory regions, types and attributes on page 2-10 for moreinformation.2.1.6 The Cortex Microcontroller Software Interface StandardARM provides the Cortex Microcontroller Software Interface Standard (CMSIS) forprogramming Cortex-M0+ microcontrollers. CMSIS is an integrated part of the device driverlibrary. For a Cortex-M0+ microcontroller system, CMSIS defines:• a common way to:— access peripheral registers— define exception vectors.• the names of:— the registers of the core peripherals— the core exception vectors.• a device-independent interface for RTOS kernels.CMSIS includes address definitions and data structures for the core peripherals in theCortex-M0+ processor. It also includes optional interfaces for middleware componentscomprising a TCP/IP stack and a Flash file system.CMSIS simplifies software development by enabling the reuse of template code, and thecombination of CMSIS-compliant software components from various middleware vendors.Software vendors can expand CMSIS to include their peripheral definitions and accessfunctions for those peripherals.This document includes the register names defined by CMSIS, and gives short descriptions ofCMSIS functions that address the processor core and the core peripherals.NoteThis document uses the register short names defined by CMSIS. In a few cases these differ fromthe architectural short names that might be used in other documents.The following sections give more information about CMSIS:• Power management programming hints on page 2-24• Intrinsic functions on page 3-5• NVIC programming hints on page 4-7.ARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 2-9ID041812Non-Confidential
Page 1 and 2: Cortex-M0+ DevicesGeneric User Guid
Page 3: ContentsCortex-M0+ Devices Generic
Page 7 and 8: PrefaceTypographical ConventionsThe
Page 9 and 10: Chapter 1IntroductionThis chapter i
Page 11 and 12: IntroductionThe tight integration o
Page 13 and 14: Chapter 2The Cortex-M0+ ProcessorTh
Page 15 and 16: The Cortex-M0+ ProcessorIn Thread m
Page 17 and 18: The Cortex-M0+ ProcessorAccess thes
Page 19: The Cortex-M0+ ProcessorInterruptib
Page 23 and 24: The Cortex-M0+ ProcessorThe differe
Page 25 and 26: The Cortex-M0+ ProcessorTable 2-10
Page 27 and 28: The Cortex-M0+ ProcessorLittle-endi
Page 29 and 30: The Cortex-M0+ ProcessorSysTickInte
Page 31 and 32: The Cortex-M0+ ProcessorIf software
Page 33 and 34: The Cortex-M0+ ProcessorThe process
Page 35 and 36: The Cortex-M0+ Processor2.5 Power m
Page 37 and 38: Chapter 3The Cortex-M0+ Instruction
Page 39 and 40: The Cortex-M0+ Instruction SetTable
Page 41 and 42: The Cortex-M0+ Instruction Set3.2 I
Page 43 and 44: The Cortex-M0+ Instruction SetNote
Page 45 and 46: The Cortex-M0+ Instruction Set3.3.5
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The Cortex-M0+ Instruction Set3.7.1
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Chapter 4Cortex-M0+ PeripheralsThe
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Cortex-M0+ Peripherals4.2 Nested Ve
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Cortex-M0+ PeripheralsThe bit assig
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Cortex-M0+ Peripherals4.2.7 NVIC us
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Cortex-M0+ PeripheralsBits Name Fun
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Cortex-M0+ PeripheralsTable 4-11 IC
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Cortex-M0+ PeripheralsSystem Handle
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Cortex-M0+ PeripheralsTable 4-20 SY
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Cortex-M0+ Peripherals4.5 Memory Pr
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Cortex-M0+ PeripheralsSee the regis
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Cortex-M0+ PeripheralsTable 4-29 MP
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Cortex-M0+ PeripheralsThe smallest
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Cortex-M0+ Peripheralsbit controls
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Cortex-M0+ Devices Generic User Guide - Keil

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