Cortex-M0+ Devices Generic User Guide - Keil

The Cortex-M0+ Instruction Set3.4 Memory access instructionsTable 3-5 shows the memory access instructions:Table 3-5 Memory access instructionsMnemonic Brief description SeeADR Generate PC-relative address ADR on page 3-12LDM Load Multiple registers LDM and STM on page 3-16LDR{type} Load Register using immediate offset LDR and STR, immediate offset on page 3-13LDR{type} Load Register using register offset LDR and STR, register offset on page 3-14LDR Load Register from PC-relative address LDR, PC-relative on page 3-15POP Pop registers from stack PUSH and POP on page 3-18PUSH Push registers onto stack PUSH and POP on page 3-18STM Store Multiple registers LDM and STM on page 3-16STR{type} Store Register using immediate offset LDR and STR, immediate offset on page 3-13STR{type} Store Register using register offset LDR and STR, register offset on page 3-14ARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 3-11ID041812Non-Confidential