Cortex-M0+ Devices Generic User Guide - Keil

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The Cortex-M0+ Instruction Set3.7.6 MRSMove the contents of a special register to a general-purpose register.SyntaxMRS Rd, spec_regwhere:Rdspec_regIs the general-purpose destination register.Is one of the special-purpose registers: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR,MSP, PSP, PRIMASK, or CONTROL.OperationMRS stores the contents of a special-purpose register to a general-purpose register. The MRSinstruction can be combined with the MSR instruction to produce read-modify-write sequences,that are suitable for modifying a specific flag in the PSR.See MSR on page 3-43.RestrictionsIn this instruction, Rd must not be SP or PC.If the current mode of execution is not privileged, then the values of all registers other than theAPSR read as zero.Condition flagsThis instruction does not change the flags.ExamplesMRSR0, PRIMASK ; Read PRIMASK value and write it to R0ARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 3-42ID041812Non-Confidential
The Cortex-M0+ Instruction Set3.7.7 MSRMove the contents of a general-purpose register into the specified special register.SyntaxMSR spec_reg, Rnwhere:Rnspec_regIs the general-purpose source register.Is the special-purpose destination register: APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR,PSR, MSP, PSP, PRIMASK, or CONTROL.OperationMSR updates one of the special registers with the value from the register specified by Rn.See MRS on page 3-42.RestrictionsIn this instruction, Rn must not be SP and must not be PC.If the current mode of execution is not privileged, then all attempts to modify any register otherthan the APSR are ignored.Condition flagsThis instruction updates the flags explicitly based on the value in Rn.ExamplesMSRCONTROL, R1 ; Read R1 value and write it to the CONTROL registerARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 3-43ID041812Non-Confidential
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Cortex-M0+ DevicesGeneric User Guid
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ContentsCortex-M0+ Devices Generic
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PrefaceTypographical ConventionsThe
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Chapter 1IntroductionThis chapter i
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IntroductionThe tight integration o
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Chapter 2The Cortex-M0+ ProcessorTh
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The Cortex-M0+ ProcessorIn Thread m
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The Cortex-M0+ ProcessorAccess thes
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The Cortex-M0+ ProcessorInterruptib
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The Cortex-M0+ Processor2.1.5 Data
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The Cortex-M0+ ProcessorThe differe
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The Cortex-M0+ ProcessorTable 2-10
Page 27 and 28: The Cortex-M0+ ProcessorLittle-endi
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Page 37 and 38: Chapter 3The Cortex-M0+ Instruction
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Cortex-M0+ Devices Generic User Guide - Keil

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