Cortex-M0+ Devices Generic User Guide - Keil

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The Cortex-M0+ Processor2.3 Exception modelThis section describes the exception model.2.3.1 Exception statesEach exception is in one of the following states:InactivePendingActiveThe exception is not active and not pending.The exception is waiting to be serviced by the processor.An interrupt request from a peripheral or from software can change thestate of the corresponding interrupt to pending.The exception is being serviced by the processor but has not completed.NoteAn exception handler can interrupt the execution of another exceptionhandler. In this case both exceptions are in the active state.2.3.2 Exception typesActive and pendingThe exception is being serviced by the processor and there is a pendingexception from the same source.The exception types are:ResetNMIHardFaultSVCallPendSVReset is invoked on power up or a warm reset. The exception model treatsreset as a special form of exception. When reset is asserted, the operationof the processor stops, potentially at any point in an instruction. Whenreset is deasserted, execution restarts from the address provided by thereset entry in the vector table. Execution restarts as privileged executionin Thread mode.A Non-Maskable Interrupt (NMI) can be signalled by a peripheral ortriggered by software. This is the highest priority exception other thanreset. It is permanently enabled and has a fixed priority of –2. NMIs cannotbe:• masked or prevented from activation by any other exception• preempted by any exception other than Reset.A HardFault is an exception that occurs because of an error. HardFaultshave a fixed priority of –1, meaning they have higher priority than anyexception with configurable priority.A Supervisor Call (SVC) is an exception that is triggered by the SVCinstruction. In an OS environment, applications can use SVC instructions toaccess OS kernel functions and device drivers.PendSV is an interrupt-driven request for system-level service. In an OSenvironment, use PendSV for context switching when no other exceptionis active.ARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 2-16ID041812Non-Confidential
The Cortex-M0+ ProcessorSysTickInterrupt (IRQ)If the device implements the SysTick timer, a SysTick exception isgenerated when the SysTick timer reaches zero. Software can alsogenerate a SysTick exception. In an OS environment, the processor canuse this exception as system tick.An interrupt, or IRQ, is an exception signalled by a peripheral, orgenerated by a software request. All interrupts are asynchronous toinstruction execution. In the system, peripherals use interrupts tocommunicate with the processor.Table 2-11 Properties of the different exception typesExceptionnumber aIRQnumber a Exception type Priority Vector address b Activation1 - Reset –3, the highest 0x00000004 Asynchronous2 –14 NMI –2 0x00000008 Asynchronous3 –13 HardFault –1 0x0000000C Synchronous4-10 - Reserved - - -11 –5 SVCall Configurable e 0x0000002C Synchronous12-13 - Reserved - - -14 –2 PendSV Configurable e 0x00000038 Asynchronous15 –1 SysTick c Configurable e 0x0000003C Asynchronous15 - Reserved - - -16 and above d 0 and above Interrupt (IRQ) Configurable e 0x00000040 and above f Asynchronousa. To simplify the software layer, CMSIS only uses IRQ numbers and therefore uses negative values for exceptions otherthan interrupts. The IPSR returns the Exception number, see Interrupt Program Status Register on page 2-6.b. See Vector table on page 2-18 for more information.c. If your device does not implement the SysTick timer, exception number 15 is reserved.d. The number of IRQ interrupts is implementation-defined, in the range 0-32. Unimplemented IRQ exception numbersare reserved, for example if the device implements only one IRQ, exception numbers 17 and above are reserved.e. See Interrupt Priority Registers on page 4-5.f. Increasing in steps of 4.For an asynchronous exception, other than reset, the processor can execute additionalinstructions between when the exception is triggered and when the processor enters theexception handler.Privileged software can disable the exceptions that Table 2-11 shows as having configurablepriority, see Interrupt Clear-Enable Register on page 4-4.For more information about HardFaults, see Fault handling on page 2-22.2.3.3 Exception handlersThe processor handles exceptions using:Interrupt Service Routines (ISRs)The IRQ interrupts are the exceptions handled by ISRs.Fault handlerHardFault is the only exception handled by the fault handler.ARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 2-17ID041812Non-Confidential
Page 1 and 2: Cortex-M0+ DevicesGeneric User Guid
Page 3: ContentsCortex-M0+ Devices Generic
Page 7 and 8: PrefaceTypographical ConventionsThe
Page 9 and 10: Chapter 1IntroductionThis chapter i
Page 11 and 12: IntroductionThe tight integration o
Page 13 and 14: Chapter 2The Cortex-M0+ ProcessorTh
Page 15 and 16: The Cortex-M0+ ProcessorIn Thread m
Page 17 and 18: The Cortex-M0+ ProcessorAccess thes
Page 19 and 20: The Cortex-M0+ ProcessorInterruptib
Page 21 and 22: The Cortex-M0+ Processor2.1.5 Data
Page 23 and 24: The Cortex-M0+ ProcessorThe differe
Page 25 and 26: The Cortex-M0+ ProcessorTable 2-10
Page 27: The Cortex-M0+ ProcessorLittle-endi
Page 31 and 32: The Cortex-M0+ ProcessorIf software
Page 33 and 34: The Cortex-M0+ ProcessorThe process
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Page 37 and 38: Chapter 3The Cortex-M0+ Instruction
Page 39 and 40: The Cortex-M0+ Instruction SetTable
Page 41 and 42: The Cortex-M0+ Instruction Set3.2 I
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Cortex-M0+ Devices Generic User Guide - Keil

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