Cortex-M0+ Devices Generic User Guide - Keil

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The Cortex-M0+ Instruction Set3.4.5 LDM and STMLoad and Store Multiple registers.SyntaxLDM Rn{!}, reglistSTM Rn!, reglistwhere:RnIs the register on which the memory addresses are based.! Writeback suffix.reglistIs a list of one or more registers to be loaded or stored, enclosed in braces. It cancontain register ranges. It must be comma separated if it contains more than oneregister or register range, see Examples on page 3-17.LDMIA and LDMFD are synonyms for LDM. LDMIA refers to the base register being Incremented Aftereach access. LDMFD refers to its use for popping data from Full Descending stacks.STMIA and STMEA are synonyms for STM. STMIA refers to the base register being Incremented Aftereach access. STMEA refers to its use for pushing data onto Empty Ascending stacks.OperationLDM instructions load the registers in reglist with word values from memory addresses based onRn.STM instructions store the word values in the registers in reglist to memory addresses based onRn.The memory addresses used for the accesses are at 4-byte intervals ranging from the value inthe register specified by Rn to the value in the register specified by Rn + 4 * (n-1), where n is thenumber of registers in reglist. The accesses happens in order of increasing register numbers,with the lowest numbered register using the lowest memory address and the highest numberregister using the highest memory address. If the writeback suffix is specified, the value in theregister specified by Rn + 4 *n is written back to the register specified by Rn.RestrictionsIn these instructions:• reglist and Rn are limited to R0-R7.• the writeback suffix must always be used unless the instruction is an LDM where reglist alsocontains Rn, in which case the writeback suffix must not be used.• the value in the register specified by Rn must be word aligned. See Address alignment onpage 3-8 for more information.• for STM, if Rn appears in reglist, then it must be the first register in the list.Condition flagsThese instructions do not change the flags.ARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 3-16ID041812Non-Confidential
The Cortex-M0+ Instruction SetExamplesLDM R0,{R0,R3,R4} ; LDMIA is a synonym for LDMSTMIA R1!,{R2-R4,R6}Incorrect examplesSTM R5!,{R4,R5,R6} ; Value stored for R5 is unpredictableLDM R2,{} ; There must be at least one register in the listARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 3-17ID041812Non-Confidential
Page 1 and 2: Cortex-M0+ DevicesGeneric User Guid
Page 3: ContentsCortex-M0+ Devices Generic
Page 7 and 8: PrefaceTypographical ConventionsThe
Page 9 and 10: Chapter 1IntroductionThis chapter i
Page 11 and 12: IntroductionThe tight integration o
Page 13 and 14: Chapter 2The Cortex-M0+ ProcessorTh
Page 15 and 16: The Cortex-M0+ ProcessorIn Thread m
Page 17 and 18: The Cortex-M0+ ProcessorAccess thes
Page 19 and 20: The Cortex-M0+ ProcessorInterruptib
Page 21 and 22: The Cortex-M0+ Processor2.1.5 Data
Page 23 and 24: The Cortex-M0+ ProcessorThe differe
Page 25 and 26: The Cortex-M0+ ProcessorTable 2-10
Page 27 and 28: The Cortex-M0+ ProcessorLittle-endi
Page 29 and 30: The Cortex-M0+ ProcessorSysTickInte
Page 31 and 32: The Cortex-M0+ ProcessorIf software
Page 33 and 34: The Cortex-M0+ ProcessorThe process
Page 35 and 36: The Cortex-M0+ Processor2.5 Power m
Page 37 and 38: Chapter 3The Cortex-M0+ Instruction
Page 39 and 40: The Cortex-M0+ Instruction SetTable
Page 41 and 42: The Cortex-M0+ Instruction Set3.2 I
Page 43 and 44: The Cortex-M0+ Instruction SetNote
Page 45 and 46: The Cortex-M0+ Instruction Set3.3.5
Page 47 and 48: The Cortex-M0+ Instruction Set3.4 M
Page 51: The Cortex-M0+ Instruction Set3.4.4
Page 55 and 56: The Cortex-M0+ Instruction Set3.5 G
Page 57 and 58: The Cortex-M0+ Instruction SetRestr
Page 61 and 62: The Cortex-M0+ Instruction SetExamp
Page 69 and 70: The Cortex-M0+ Instruction Set3.6 B
Page 71 and 72: The Cortex-M0+ Instruction SetCondi
Page 85 and 86: Chapter 4Cortex-M0+ PeripheralsThe
Page 87 and 88: Cortex-M0+ Peripherals4.2 Nested Ve
Page 89 and 90: Cortex-M0+ PeripheralsThe bit assig
Page 91 and 92: Cortex-M0+ Peripherals4.2.7 NVIC us
Page 93 and 94: Cortex-M0+ PeripheralsBits Name Fun
Page 95 and 96: Cortex-M0+ PeripheralsTable 4-11 IC
Page 97 and 98: Cortex-M0+ PeripheralsTable 4-13 AI
Page 99 and 100: Cortex-M0+ PeripheralsSystem Handle
Page 101 and 102: Cortex-M0+ PeripheralsTable 4-20 SY
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Cortex-M0+ Peripherals4.5 Memory Pr
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Cortex-M0+ PeripheralsSee the regis
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Cortex-M0+ PeripheralsTable 4-29 MP
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Cortex-M0+ PeripheralsThe smallest
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Cortex-M0+ Peripheralsbit controls
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Cortex-M0+ Devices Generic User Guide - Keil

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