Cortex-M0+ Devices Generic User Guide - Keil

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Cortex-M0+ PeripheralsUse the MPU registers to define the MPU regions and their attributes. Table 4-25 shows theMPU registers.Table 4-25 MPU registers summaryAddress Name TypeResetvalueDescription0xE000ED90 MPU_TYPE RO 0x00000800 MPU Type Register0xE000ED94 MPU_CTRL RW 0x00000000 MPU Control Register0xE000ED98 MPU_RNR RW 0x00000000 MPU Region Number Register on page 4-220xE000ED9C MPU_RBAR RW 0x00000000 MPU Region Base Address Register on page 4-220xE000EDA0 MPU_RASR RW 0x00000000 MPU Region Attribute and Size Register on page 4-234.5.1 MPU Type RegisterThe MPU_TYPE register indicates whether the MPU is present, and if so, how many regions itsupports. See the register summary in Table 4-25 for its attributes. The bit assignments are:31 24 23 16 15 8 7 1 0ReservedIREGION DREGION ReservedSEPARATETable 4-26 MPU_TYPE register bit assignmentsBits Name Function[31:24] - Reserved.[23:16] IREGION Indicates the number of supported MPU instruction regions.Always contains 0x00. The MPU memory map is unified and is described by the DREGION field.[15:8] DREGION Indicates the number of supported MPU data regions:0x08 = Eight MPU regions.[7:1] - Reserved.[0] SEPARATE Indicates support for unified or separate instruction and date memory maps:0 = unified.4.5.2 MPU Control RegisterThe MPU_CTRL register:• enables the MPU• enables the default memory map background region• enables use of the MPU when in the HardFault and Non-Maskable Interrupt (NMI).ARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 4-20ID041812Non-Confidential
Cortex-M0+ PeripheralsSee the register summary in Table 4-25 on page 4-20 for the MPU_CTRL attributes. The bitassignments are:31 3 2 1 0ReservedPRIVDEFENAHFNMIENAENABLETable 4-27 MPU_CTRL register bit assignmentsBits Name Function[31:3] - Reserved.[2] PRIVDEFENA Enables privileged software access to the default memory map:0 = If the MPU is enabled, disables use of the default memory map. Any memory access to a location notcovered by any enabled region causes a fault.1 = If the MPU is enabled, enables use of the default memory map as a background region for privilegedsoftware accesses.When enabled, the background region acts as if it is region number -1. Any region that is defined andenabled has priority over this default map.If the MPU is disabled, the processor ignores this bit.[1] HFNMIENA Enables the operation of MPU during HardFault and NMI handlers.When the MPU is enabled:0 = MPU is disabled during HardFault and NMI handlers, regardless of the value of the ENABLE bit1 = the MPU is enabled during HardFault and NMI handlers.When the MPU is disabled, if this bit is set to 1 the behavior is Unpredictable.[0] ENABLE Enables the MPU:0 = MPU disabled1 = MPU enabled.When ENABLE and PRIVDEFENA are both set to 1:• For privileged accesses, the default memory map is as described in Memory model onpage 2-10. Any access by privileged software that does not address an enabled memoryregion behaves as defined by the default memory map.• Any access by unprivileged software that does not address an enabled memory regioncauses a HardFault.XN and Strongly-ordered rules always apply to the System Control Space regardless of thevalue of the ENABLE bit.When the ENABLE bit is set to 1, at least one region of the memory map must be enabled forthe system to function unless the PRIVDEFENA bit is set to 1. If the PRIVDEFENA bit is setto 1 and no regions are enabled, then only privileged software can operate.When the ENABLE bit is set to 0, the system uses the default memory map. This has the samememory attributes as if the MPU is not implemented, see Table 2-9 on page 2-12. The defaultmemory map applies to accesses from both privileged and unprivileged software.When the MPU is enabled, accesses to the System Control Space and vector table are alwayspermitted. Other areas are accessible based on regions and whether PRIVDEFENA is set to 1.ARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 4-21ID041812Non-Confidential
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Cortex-M0+ DevicesGeneric User Guid
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ContentsCortex-M0+ Devices Generic
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PrefaceTypographical ConventionsThe
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Chapter 1IntroductionThis chapter i
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IntroductionThe tight integration o
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Chapter 2The Cortex-M0+ ProcessorTh
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The Cortex-M0+ ProcessorIn Thread m
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The Cortex-M0+ ProcessorAccess thes
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The Cortex-M0+ ProcessorInterruptib
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The Cortex-M0+ Processor2.1.5 Data
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The Cortex-M0+ ProcessorThe differe
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The Cortex-M0+ ProcessorTable 2-10
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The Cortex-M0+ ProcessorLittle-endi
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The Cortex-M0+ ProcessorSysTickInte
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The Cortex-M0+ ProcessorIf software
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The Cortex-M0+ ProcessorThe process
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The Cortex-M0+ Processor2.5 Power m
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Chapter 3The Cortex-M0+ Instruction
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The Cortex-M0+ Instruction SetTable
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The Cortex-M0+ Instruction Set3.2 I
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The Cortex-M0+ Instruction SetNote
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The Cortex-M0+ Instruction Set3.3.5
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The Cortex-M0+ Instruction Set3.4 M
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Cortex-M0+ Devices Generic User Guide - Keil

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