Cortex-M0+ Devices Generic User Guide - Keil

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The Cortex-M0+ Processor2.2.3 Behavior of memory accessesThe behavior of accesses to each region in the default memory map is:Table 2-9 Memory access behaviorAddressrangeMemoryregionMemorytype a XN a Description0x00000000-0x1FFFFFFF0x20000000-0x3FFFFFFF0x40000000-0x5FFFFFFF0x60000000-0x9FFFFFFFCode Normal - Executable region for program code. You can also put data here.SRAM Normal - Executable region for data. You can also put code here.Peripheral Device XN External device memory.External RAM Normal - Executable region for data.0xA0000000-0xDFFFFFFFExternaldeviceDevice XN External device memory.0xE0000000-0xE00FFFFFPrivatePeripheral BusStronglyorderedXNThis region includes the NVIC, System timer, and System Control Block.Only word accesses can be used in this region.0xE0100000-0xFFFFFFFFSystem Device XN Vendor specific.a. See Memory regions, types and attributes on page 2-10 for more information.The Code, SRAM, and external RAM regions can hold programs.The optional MPU can override the default memory access behavior described in this section.For more information, see Memory Protection Unit on page 4-19.Additional memory access constraints for caches and shared memoryWhen a system includes caches or shared memory, some memory regions have additional accessconstraints, and some regions are subdivided, as Table 2-10 shows:Table 2-10 Memory region shareability and cache policiesAddress range Memory region Memory type a Shareability a Cache policy b0x00000000- 0x1FFFFFFF Code Normal - WT0x20000000- 0x3FFFFFFF SRAM Normal - WBWA0x40000000- 0x5FFFFFFF Peripheral Device - -0x60000000- 0x7FFFFFFF External RAM Normal - WBWA0x80000000- 0x9FFFFFFF WTARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 2-12ID041812Non-Confidential
The Cortex-M0+ ProcessorTable 2-10 Memory region shareability and cache policies (continued)Address range Memory region Memory type a Shareability a Cache policy b0xA0000000- 0xBFFFFFFF External device Device Shareable -0xC0000000- 0xDFFFFFFF0xE0000000- 0xE00FFFFFPrivate PeripheralBusNon-shareableStrongly- ordered Shareable -0xE0100000- 0xFFFFFFFF System Device - -a. See Memory regions, types and attributes on page 2-10 for more information.b. WT = Write through, no write allocate. WBWA = Write back, write allocate.2.2.4 Software ordering of memory accessesThe order of instructions in the program flow does not always guarantee the order of thecorresponding memory transactions. This is because:• a processor can reorder some memory accesses to improve efficiency, providing this doesnot affect the behavior of the instruction sequence• memory or devices in the memory map might have different wait states• some memory accesses are buffered or speculative.Memory system ordering of memory accesses on page 2-11 describes the cases where thememory system guarantees the order of memory accesses. Otherwise, if the order of memoryaccesses is critical, software must include memory barrier instructions to force that ordering.The processor provides the following memory barrier instructions:DMBDSBISBThe Data Memory Barrier (DMB) instruction ensures that outstandingmemory transactions complete before subsequent memory transactions.See DMB on page 3-39.The Data Synchronization Barrier (DSB) instruction ensures thatoutstanding memory transactions complete before subsequent instructionsexecute. See DSB on page 3-40.The Instruction Synchronization Barrier (ISB) ensures that the effect of allcompleted memory transactions is recognizable by subsequentinstructions. See ISB on page 3-41.The following are examples of using memory barrier instructions:Vector tableIf the program changes an entry in the vector table, and then enables thecorresponding exception, use a DMB instruction between the operations.This ensures that if the exception is taken immediately after being enabledthe processor uses the new exception vector.Self-modifying codeIf a program contains self-modifying code, use a DSB instruction, followedby an ISB instruction, immediately after the code modification in theprogram. This ensures subsequent instruction execution uses the updatedprogram.ARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 2-13ID041812Non-Confidential
Page 1 and 2: Cortex-M0+ DevicesGeneric User Guid
Page 3: ContentsCortex-M0+ Devices Generic
Page 7 and 8: PrefaceTypographical ConventionsThe
Page 9 and 10: Chapter 1IntroductionThis chapter i
Page 11 and 12: IntroductionThe tight integration o
Page 13 and 14: Chapter 2The Cortex-M0+ ProcessorTh
Page 15 and 16: The Cortex-M0+ ProcessorIn Thread m
Page 17 and 18: The Cortex-M0+ ProcessorAccess thes
Page 19 and 20: The Cortex-M0+ ProcessorInterruptib
Page 21 and 22: The Cortex-M0+ Processor2.1.5 Data
Page 23: The Cortex-M0+ ProcessorThe differe
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Page 29 and 30: The Cortex-M0+ ProcessorSysTickInte
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Page 37 and 38: Chapter 3The Cortex-M0+ Instruction
Page 39 and 40: The Cortex-M0+ Instruction SetTable
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Cortex-M0+ Devices Generic User Guide - Keil

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