Cortex-M0+ Devices Generic User Guide - Keil

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Cortex-M0+ PeripheralsThe bit assignments are:31 29 28 27 26 24 23 19 18 17 16 15 8 7 6 5 1 0AP Reserved S C B SRD SIZEReservedXNReservedReservedENABLETable 4-30 MPU_RASR bit assignmentsBits Name Function[31:29] - Reserved.[28] XN Instruction access disable bit:0 = instruction fetches enabled1 = instruction fetches disabled.[27] - Reserved.[26:24] AP Access permission field, see Table 4-33 on page 4-25.[23:19] - Reserved.[18] S Shareable bit, see Table 4-32 on page 4-25.[17] C Cacheable bit, see Table 4-32 on page 4-25.[16] B Bufferable bit, see Table 4-32 on page 4-25.[15:8] SRD Subregion disable bits. For each bit in this field:0 = corresponding sub-region is enabled1 = corresponding sub-region is disabled.See Subregions on page 4-26 for more information.[7:6] - Reserved.[5:1] SIZE Specifies the size of the MPU protection region. The minimum permitted value is 7 (b00111).See SIZE field values for more information.[0] ENABLE Region enable bit.For information about access permission, see MPU access permission attributes on page 4-25.SIZE field valuesThe SIZE field defines the size of the MPU memory region specified by the MPU_RNR, asfollows:(Region size in bytes) = 2 (SIZE+1)ARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 4-24ID041812Non-Confidential
Cortex-M0+ PeripheralsThe smallest permitted region size is 256B, corresponding to a SIZE value of 7. Table 4-31gives example SIZE values, with the corresponding region size and value of N in theMPU_RBAR.Table 4-31 Example SIZE field valuesSIZE value Region size Value of N aNoteb00111 (7) 256B 8 Minimum permitted sizeb01001 (9) 1KB 10 -b10011 (19) 1MB 20 -b11101 (29) 1GB 30 -b11111 (31) 4GB 32 Maximum possible sizea. In the MPU_RBAR, see MPU Region Base Address Register on page 4-22.4.5.6 MPU access permission attributesThis section describes the MPU access permission attributes. The access permission bits, C, B,S, AP, and XN, of the MPU_RASR, control access to the corresponding memory region. If anaccess is made to an area of memory without the required permissions, then the MPU generatesa permission fault.Table 4-32 shows the encodings for the C, B, and S access permission bits.C B S Memory type Shareability Other attributesTable 4-32 C, B, and S encoding0 0 x aStrongly-ordered Shareable -1 x a Device Shareable -1 0 0 Normal Not shareable Outer and inner write-through. No write allocate.1 Shareable1 0 Normal Not shareable Outer and inner write-back. No write allocate.1 Shareablea. The MPU ignores the value of this bit.Table 4-33 shows the AP encodings that define the access permissions for privileged andunprivileged software.Table 4-33 AP encodingAP[2:0]PrivilegedpermissionsUnprivilegedpermissionsDescription000 No access No access All accesses generate a permission fault001 RW No access Access from privileged software only010 RW RO Writes by unprivileged software generate a permission fault011 RW RW Full accessARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 4-25ID041812Non-Confidential
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Cortex-M0+ DevicesGeneric User Guid
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ContentsCortex-M0+ Devices Generic
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PrefaceTypographical ConventionsThe
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Chapter 1IntroductionThis chapter i
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IntroductionThe tight integration o
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Chapter 2The Cortex-M0+ ProcessorTh
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The Cortex-M0+ ProcessorIn Thread m
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The Cortex-M0+ ProcessorAccess thes
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The Cortex-M0+ ProcessorInterruptib
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The Cortex-M0+ Processor2.1.5 Data
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The Cortex-M0+ ProcessorThe differe
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The Cortex-M0+ ProcessorTable 2-10
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The Cortex-M0+ ProcessorLittle-endi
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The Cortex-M0+ ProcessorSysTickInte
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The Cortex-M0+ ProcessorIf software
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The Cortex-M0+ ProcessorThe process
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The Cortex-M0+ Processor2.5 Power m
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Chapter 3The Cortex-M0+ Instruction
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The Cortex-M0+ Instruction SetTable
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The Cortex-M0+ Instruction Set3.2 I
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The Cortex-M0+ Instruction SetNote
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The Cortex-M0+ Instruction Set3.3.5
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The Cortex-M0+ Instruction Set3.4 M
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Cortex-M0+ Devices Generic User Guide - Keil

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