Cortex-M0+ Devices Generic User Guide - Keil

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The Cortex-M0+ Instruction Set3.5.1 ADC, ADD, RSB, SBC, and SUBAdd with carry, Add, Reverse Subtract, Subtract with carry, and Subtract.SyntaxADCS {Rd,} Rn, RmADD{S} {Rd,} Rn, RSBS {Rd,} Rn, Rm, #0SBCS {Rd,} Rn, RmSUB{S} {Rd,} Rn, Where:SRdRnRmimmCauses an ADD or SUB instruction to update flagsSpecifies the result registerSpecifies the first source registerSpecifies the second source registerSpecifies a constant immediate value.When the optional Rd register specifier is omitted, it is assumed to take the same value as Rn, forexample ADDS R1,R2 is identical to ADDS R1,R1,R2.OperationThe ADCS instruction adds the value in Rn to the value in Rm, adding another one if the carry flagis set, places the result in the register specified by Rd and updates the N, Z, C, and V flags.The ADD instruction adds the value in Rn to the value in Rm or an immediate value specified by immand places the result in the register specified by Rd.The ADDS instruction performs the same operation as ADD and also updates the N, Z, C and Vflags.The RSBS instruction subtracts the value in Rn from zero, producing the arithmetic negative of thevalue, and places the result in the register specified by Rd and updates the N, Z, C and V flags.The SBCS instruction subtracts the value of Rm from the value in Rn, deducts another one if thecarry flag is set. It places the result in the register specified by Rd and updates the N, Z, C andV flags.The SUB instruction subtracts the value in Rm or the immediate specified by imm. It places theresult in the register specified by Rd.The SUBS instruction performs the same operation as SUB and also updates the N, Z, C and Vflags.Use ADC and SBC to synthesize multiword arithmetic, see Examples on page 3-22.See also ADR on page 3-12.ARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 3-20ID041812Non-Confidential
The Cortex-M0+ Instruction SetRestrictionsTable 3-7 lists the legal combinations of register specifiers and immediate values that can beused with each instruction.Instruction Rd Rn Rm imm RestrictionsTable 3-7 ADC, ADD, RSB, SBC and SUB operand restrictionsADCS R0-R7 R0-R7 R0-R7 - Rd and Rn must specify the same register.ADD R0-R15 R0-R15 R0-PC - Rd and Rn must specify the same register.Rn and Rm must not both specify PC.R0-R7 SP or PC - 0-1020 Immediate value must be an integer multiple of four.SP SP - 0-508 Immediate value must be an integer multiple of four.ADDS R0-R7 R0-R7 - 0-7 -R0-R7 R0-R7 - 0-255 Rd and Rn must specify the same register.R0-R7 R0-R7 R0-R7 - -RSBS R0-R7 R0-R7 - - -SBCS R0-R7 R0-R7 R0-R7 - Rd and Rn must specify the same register.SUB SP SP - 0-508 Immediate value must be an integer multiple of four.SUBS R0-R7 R0-R7 - 0-7 -R0-R7 R0-R7 - 0-255 Rd and Rn must specify the same register.R0-R7 R0-R7 R0-R7 - -ARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 3-21ID041812Non-Confidential
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Cortex-M0+ DevicesGeneric User Guid
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ContentsCortex-M0+ Devices Generic
Page 7 and 8: PrefaceTypographical ConventionsThe
Page 9 and 10: Chapter 1IntroductionThis chapter i
Page 11 and 12: IntroductionThe tight integration o
Page 13 and 14: Chapter 2The Cortex-M0+ ProcessorTh
Page 15 and 16: The Cortex-M0+ ProcessorIn Thread m
Page 17 and 18: The Cortex-M0+ ProcessorAccess thes
Page 19 and 20: The Cortex-M0+ ProcessorInterruptib
Page 21 and 22: The Cortex-M0+ Processor2.1.5 Data
Page 23 and 24: The Cortex-M0+ ProcessorThe differe
Page 25 and 26: The Cortex-M0+ ProcessorTable 2-10
Page 27 and 28: The Cortex-M0+ ProcessorLittle-endi
Page 29 and 30: The Cortex-M0+ ProcessorSysTickInte
Page 31 and 32: The Cortex-M0+ ProcessorIf software
Page 33 and 34: The Cortex-M0+ ProcessorThe process
Page 35 and 36: The Cortex-M0+ Processor2.5 Power m
Page 37 and 38: Chapter 3The Cortex-M0+ Instruction
Page 39 and 40: The Cortex-M0+ Instruction SetTable
Page 41 and 42: The Cortex-M0+ Instruction Set3.2 I
Page 43 and 44: The Cortex-M0+ Instruction SetNote
Page 45 and 46: The Cortex-M0+ Instruction Set3.3.5
Page 47 and 48: The Cortex-M0+ Instruction Set3.4 M
Page 53 and 54: The Cortex-M0+ Instruction SetExamp
Page 55: The Cortex-M0+ Instruction Set3.5 G
Page 61 and 62: The Cortex-M0+ Instruction SetExamp
Page 69 and 70: The Cortex-M0+ Instruction Set3.6 B
Page 71 and 72: The Cortex-M0+ Instruction SetCondi
Page 85 and 86: Chapter 4Cortex-M0+ PeripheralsThe
Page 87 and 88: Cortex-M0+ Peripherals4.2 Nested Ve
Page 89 and 90: Cortex-M0+ PeripheralsThe bit assig
Page 91 and 92: Cortex-M0+ Peripherals4.2.7 NVIC us
Page 93 and 94: Cortex-M0+ PeripheralsBits Name Fun
Page 95 and 96: Cortex-M0+ PeripheralsTable 4-11 IC
Page 97 and 98: Cortex-M0+ PeripheralsTable 4-13 AI
Page 99 and 100: Cortex-M0+ PeripheralsSystem Handle
Page 101 and 102: Cortex-M0+ PeripheralsTable 4-20 SY
Page 103 and 104: Cortex-M0+ Peripherals4.5 Memory Pr
Page 105 and 106: Cortex-M0+ PeripheralsSee the regis
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Cortex-M0+ PeripheralsTable 4-29 MP
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Cortex-M0+ PeripheralsThe smallest
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Cortex-M0+ Peripheralsbit controls
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Cortex-M0+ Devices Generic User Guide - Keil

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