Cortex-M0+ Devices Generic User Guide - Keil

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The Cortex-M0+ Processor2.2 Memory modelThis section describes the processor memory map and the behavior of memory accesses. Theprocessor has a default memory map that provides up to 4GB of addressable memory. Thememory map is:0xFFFFFFFFSystem511MBPrivate Peripheral Bus 1MB0xE01000000xE00FFFFF0xE00000000xDFFFFFFFExternal device1.0GB0xA00000000x9FFFFFFFExternal RAM1.0GB0x600000000x5FFFFFFFPeripheral0.5GB0x400000000x3FFFFFFFSRAM0.5GB0x200000000x1FFFFFFFCode0.5GB0x00000000The processor reserves regions of the Private Peripheral Bus (PPB) address range for coreperipheral registers, see About the Cortex-M0+ processor and core peripherals on page 1-2.2.2.1 Memory regions, types and attributesThe default memory map and the programming of the optional MPU split the address space intoregions. Each region has a defined memory type, and some regions have additional memoryattributes. The memory type and attributes determine the behavior of accesses to the region.The memory types are:NormalDeviceStrongly-orderedThe processor can re-order transactions for efficiency, or performspeculative reads.The processor preserves transaction order relative to other transactions toDevice or Strongly-ordered memory.The processor preserves transaction order relative to all other transactions.ARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 2-10ID041812Non-Confidential
The Cortex-M0+ ProcessorThe different ordering requirements for Device and Strongly-ordered memory mean that thememory system can buffer a write to Device memory, but must not buffer a write toStrongly-ordered memory.The additional memory attributes include.ShareableFor a shareable memory region, the memory system provides datasynchronization between bus masters in a system with multiple busmasters, for example, a processor with a DMA controller.Strongly-ordered memory is always shareable.If multiple bus masters can access a non-shareable memory region,software must ensure data coherency between the bus masters.NoteThis attribute is relevant only if the device is likely to be used in systemswhere memory is shared between multiple processors.Execute Never (XN)The processor cannot execute instructions in an XN region. A HardFaultexception is generated if it tries.2.2.2 Memory system ordering of memory accessesFor most memory accesses caused by explicit memory access instructions, the memory systemdoes not guarantee that the order in which the accesses complete matches the program order ofthe instructions, providing any re-ordering does not affect the behavior of the instructionsequence. Normally, if correct program execution depends on two memory accesses completingin program order, software must insert a memory barrier instruction between the memory accessinstructions, see Software ordering of memory accesses on page 2-13.However, the memory system does guarantee some ordering of accesses to Device andStrongly-ordered memory. For two memory access instructions A1 and A2, if A1 occurs beforeA2 in program order, the ordering of the memory accesses caused by two instructions is:A1A2NormalaccessDevice accessNon-shareableShareableStronglyorderedaccessNormal access----Device access, non-shareable-
Page 1 and 2: Cortex-M0+ DevicesGeneric User Guid
Page 3: ContentsCortex-M0+ Devices Generic
Page 7 and 8: PrefaceTypographical ConventionsThe
Page 9 and 10: Chapter 1IntroductionThis chapter i
Page 11 and 12: IntroductionThe tight integration o
Page 13 and 14: Chapter 2The Cortex-M0+ ProcessorTh
Page 15 and 16: The Cortex-M0+ ProcessorIn Thread m
Page 17 and 18: The Cortex-M0+ ProcessorAccess thes
Page 19 and 20: The Cortex-M0+ ProcessorInterruptib
Page 21: The Cortex-M0+ Processor2.1.5 Data
Page 25 and 26: The Cortex-M0+ ProcessorTable 2-10
Page 27 and 28: The Cortex-M0+ ProcessorLittle-endi
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Page 37 and 38: Chapter 3The Cortex-M0+ Instruction
Page 39 and 40: The Cortex-M0+ Instruction SetTable
Page 41 and 42: The Cortex-M0+ Instruction Set3.2 I
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Cortex-M0+ Peripherals4.2 Nested Ve
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Cortex-M0+ Devices Generic User Guide - Keil

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