Cortex-M0+ Devices Generic User Guide - Keil
Cortex-M0+ Devices Generic User Guide - Keil
Cortex-M0+ Devices Generic User Guide - Keil
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The <strong>Cortex</strong>-<strong>M0+</strong> Instruction Set3.7 Miscellaneous instructionsTable 3-10 shows the remaining <strong>Cortex</strong>-<strong>M0+</strong> instructions:Table 3-10 Miscellaneous instructionsMnemonic Brief description SeeBKPT Breakpoint BKPT on page 3-37CPSID Change Processor State, Disable Interrupts CPS on page 3-38CPSIE Change Processor State, Enable Interrupts CPS on page 3-38DMB Data Memory Barrier DMB on page 3-39DSB Data Synchronization Barrier DSB on page 3-40ISB Instruction Synchronization Barrier ISB on page 3-41MRS Move from special register to register MRS on page 3-42MSR Move from register to special register MSR on page 3-43NOP No Operation NOP on page 3-44SEV Send Event SEV on page 3-45SVC Supervisor Call SVC on page 3-46WFE Wait For Event WFE on page 3-47WFI Wait For Interrupt WFI on page 3-48ARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 3-36ID041812Non-Confidential
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