Cortex-M0+ Devices Generic User Guide - Keil

More documents

Recommendations

Info

The Cortex-M0+ Processor2.1 Programmers modelThis section describes the Cortex-M0+ programmers model. In addition to the individual coreregister descriptions, it contains information about the processor modes, optional privilegelevels for software execution, and stacks.2.1.1 Processor modes and privilege levels for software executionThe processor modes are:Thread modeHandler modeExecutes application software. The processor enters Thread mode when itcomes out of reset.Handles exceptions. The processor returns to Thread mode when it hasfinished all exception processing.The optional privilege levels for software execution are:UnprivilegedPrivilegedThe software:• has limited access to system registers using the MSR and MRSinstructions, and cannot use the CPS instruction to mask interrupts• cannot access the system timer, NVIC, or system control block• might have restricted access to memory or peripherals.Unprivileged software executes at the unprivileged level.The software can use all the instructions and has access to all resources.Privileged software executes at the privileged level.In Thread mode, the CONTROL register controls whether software execution is privileged orunprivileged, see CONTROL register on page 2-8. In Handler mode, software execution isalways privileged.Only privileged software can write to the CONTROL register to change the privilege level forsoftware execution in Thread mode. Unprivileged software can use the SVC instruction to makea Supervisor Call to transfer control to privileged software.2.1.2 StacksThe processor uses a full descending stack. This means the stack pointer indicates the laststacked item on the stack memory. When the processor pushes a new item onto the stack, itdecrements the stack pointer and then writes the item to the new memory location. Theprocessor implements two stacks, the main stack and the process stack, with independent copiesof the stack pointer, see Stack Pointer on page 2-4.ARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 2-2ID041812Non-Confidential
The Cortex-M0+ ProcessorIn Thread mode, the CONTROL register controls whether the processor uses the main stack orthe process stack, see CONTROL register on page 2-8. In Handler mode, the processor alwaysuses the main stack. The options for processor operations are:Table 2-1 Summary of processor mode, optional execution privilege level, and stack useoptionsProcessor modeUsed to executeOptional privilege levelfor software executionStack usedThread Applications Privileged or unprivileged a Main stack or process stack aHandler Exception handlers Always privileged Main stacka. See CONTROL register on page 2-8.2.1.3 Core registersThe processor core registers are:Low registersHigh registersActive Stack PointerLink RegisterProgram CounterR0R1R2R3R4R5R6R7R8R9R10R11R12SP (R13)LR (R14)PC (R15)General purpose registersBanked stack pointersPSPMSPPSRPRIMASKCONTROLProgram Status RegisterInterrupt mask registerControl RegisterSpecial registersTable 2-2 Core register set summaryName Type a Reset value DescriptionR0-R12 RW Unknown General-purpose registers on page 2-4MSP RW See description Stack Pointer on page 2-4PSP RW Unknown Stack Pointer on page 2-4LR RW Unknown Link Register on page 2-4PC RW See description Program Counter on page 2-4PSR RW Unknown b Program Status Register on page 2-4APSR RW Unknown Application Program Status Register on page 2-5IPSR RO 0x00000000 Interrupt Program Status Register on page 2-6ARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 2-3ID041812Non-Confidential
Page 1 and 2: Cortex-M0+ DevicesGeneric User Guid
Page 3: ContentsCortex-M0+ Devices Generic
Page 7 and 8: PrefaceTypographical ConventionsThe
Page 9 and 10: Chapter 1IntroductionThis chapter i
Page 11 and 12: IntroductionThe tight integration o
Page 13: Chapter 2The Cortex-M0+ ProcessorTh
Page 17 and 18: The Cortex-M0+ ProcessorAccess thes
Page 19 and 20: The Cortex-M0+ ProcessorInterruptib
Page 21 and 22: The Cortex-M0+ Processor2.1.5 Data
Page 23 and 24: The Cortex-M0+ ProcessorThe differe
Page 25 and 26: The Cortex-M0+ ProcessorTable 2-10
Page 27 and 28: The Cortex-M0+ ProcessorLittle-endi
Page 29 and 30: The Cortex-M0+ ProcessorSysTickInte
Page 31 and 32: The Cortex-M0+ ProcessorIf software
Page 33 and 34: The Cortex-M0+ ProcessorThe process
Page 35 and 36: The Cortex-M0+ Processor2.5 Power m
Page 37 and 38: Chapter 3The Cortex-M0+ Instruction
Page 39 and 40: The Cortex-M0+ Instruction SetTable
Page 41 and 42: The Cortex-M0+ Instruction Set3.2 I
Page 43 and 44: The Cortex-M0+ Instruction SetNote
Page 45 and 46: The Cortex-M0+ Instruction Set3.3.5
Page 47 and 48: The Cortex-M0+ Instruction Set3.4 M
Page 53 and 54: The Cortex-M0+ Instruction SetExamp
Page 55 and 56: The Cortex-M0+ Instruction Set3.5 G
Page 57 and 58: The Cortex-M0+ Instruction SetRestr
Page 61 and 62: The Cortex-M0+ Instruction SetExamp
Page 65 and 66:
The Cortex-M0+ Instruction Set3.5.6
Page 67 and 68:
Page 69 and 70:
The Cortex-M0+ Instruction Set3.6 B
Page 71 and 72:
The Cortex-M0+ Instruction SetCondi
Page 73 and 74:
Page 75 and 76:
Page 77 and 78:
Page 79 and 80:
Page 81 and 82:
Page 83 and 84:
Page 85 and 86:
Chapter 4Cortex-M0+ PeripheralsThe
Page 87 and 88:
Cortex-M0+ Peripherals4.2 Nested Ve
Page 89 and 90:
Cortex-M0+ PeripheralsThe bit assig
Page 91 and 92:
Cortex-M0+ Peripherals4.2.7 NVIC us
Page 93 and 94:
Cortex-M0+ PeripheralsBits Name Fun
Page 95 and 96:
Cortex-M0+ PeripheralsTable 4-11 IC
Page 97 and 98:
Cortex-M0+ PeripheralsTable 4-13 AI
Page 99 and 100:
Cortex-M0+ PeripheralsSystem Handle
Page 101 and 102:
Cortex-M0+ PeripheralsTable 4-20 SY
Page 103 and 104:
Cortex-M0+ Peripherals4.5 Memory Pr
Page 105 and 106:
Cortex-M0+ PeripheralsSee the regis
Page 107 and 108:
Cortex-M0+ PeripheralsTable 4-29 MP
Page 109 and 110:
Cortex-M0+ PeripheralsThe smallest
Page 111 and 112:
Cortex-M0+ Peripheralsbit controls
show all

Cortex-M0+ Devices Generic User Guide - Keil

You also want an ePaper? Increase the reach of your titles

Delete template?

Save as template?