Cortex-M0+ Devices Generic User Guide - Keil

More documents

Recommendations

Info

IntroductionOptional system timerThe system timer, SysTick, is a 24-bit count-down timer. Use this as a Real TimeOperating System (RTOS) tick timer or as a simple counter.Optional Memory Protection UnitThe Memory Protection Unit (MPU) improves system reliability by defining thememory attributes for different memory regions. It provides up to eight differentregions, and an optional predefined background region.Optional single-cycle I/O portThe single-cycle I/O port provides single-cycle loads and stores totightly-coupled peripherals.ARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 1-4ID041812Non-Confidential
Chapter 2The Cortex-M0+ ProcessorThe following sections describe the Cortex-M0+ processor:• Programmers model on page 2-2• Memory model on page 2-10• Exception model on page 2-16• Fault handling on page 2-22• Power management on page 2-23.ARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 2-1ID041812Non-Confidential
Page 1 and 2: Cortex-M0+ DevicesGeneric User Guid
Page 3: ContentsCortex-M0+ Devices Generic
Page 7 and 8: PrefaceTypographical ConventionsThe
Page 9 and 10: Chapter 1IntroductionThis chapter i
Page 11: IntroductionThe tight integration o
Page 15 and 16: The Cortex-M0+ ProcessorIn Thread m
Page 17 and 18: The Cortex-M0+ ProcessorAccess thes
Page 19 and 20: The Cortex-M0+ ProcessorInterruptib
Page 21 and 22: The Cortex-M0+ Processor2.1.5 Data
Page 23 and 24: The Cortex-M0+ ProcessorThe differe
Page 25 and 26: The Cortex-M0+ ProcessorTable 2-10
Page 27 and 28: The Cortex-M0+ ProcessorLittle-endi
Page 29 and 30: The Cortex-M0+ ProcessorSysTickInte
Page 31 and 32: The Cortex-M0+ ProcessorIf software
Page 33 and 34: The Cortex-M0+ ProcessorThe process
Page 35 and 36: The Cortex-M0+ Processor2.5 Power m
Page 37 and 38: Chapter 3The Cortex-M0+ Instruction
Page 39 and 40: The Cortex-M0+ Instruction SetTable
Page 41 and 42: The Cortex-M0+ Instruction Set3.2 I
Page 43 and 44: The Cortex-M0+ Instruction SetNote
Page 45 and 46: The Cortex-M0+ Instruction Set3.3.5
Page 47 and 48: The Cortex-M0+ Instruction Set3.4 M
Page 53 and 54: The Cortex-M0+ Instruction SetExamp
Page 55 and 56: The Cortex-M0+ Instruction Set3.5 G
Page 57 and 58: The Cortex-M0+ Instruction SetRestr
Page 61 and 62: The Cortex-M0+ Instruction SetExamp
Page 63 and 64:
The Cortex-M0+ Instruction Set3.5.5
Page 65 and 66:
Page 67 and 68:
Page 69 and 70:
The Cortex-M0+ Instruction Set3.6 B
Page 71 and 72:
The Cortex-M0+ Instruction SetCondi
Page 73 and 74:
Page 75 and 76:
Page 77 and 78:
Page 79 and 80:
Page 81 and 82:
Page 83 and 84:
Page 85 and 86:
Chapter 4Cortex-M0+ PeripheralsThe
Page 87 and 88:
Cortex-M0+ Peripherals4.2 Nested Ve
Page 89 and 90:
Cortex-M0+ PeripheralsThe bit assig
Page 91 and 92:
Cortex-M0+ Peripherals4.2.7 NVIC us
Page 93 and 94:
Cortex-M0+ PeripheralsBits Name Fun
Page 95 and 96:
Cortex-M0+ PeripheralsTable 4-11 IC
Page 97 and 98:
Cortex-M0+ PeripheralsTable 4-13 AI
Page 99 and 100:
Cortex-M0+ PeripheralsSystem Handle
Page 101 and 102:
Cortex-M0+ PeripheralsTable 4-20 SY
Page 103 and 104:
Cortex-M0+ Peripherals4.5 Memory Pr
Page 105 and 106:
Cortex-M0+ PeripheralsSee the regis
Page 107 and 108:
Cortex-M0+ PeripheralsTable 4-29 MP
Page 109 and 110:
Cortex-M0+ PeripheralsThe smallest
Page 111 and 112:
Cortex-M0+ Peripheralsbit controls
show all

Cortex-M0+ Devices Generic User Guide - Keil

Create successful ePaper yourself

Delete template?

Save as template?