Cortex-M0+ Devices Generic User Guide - Keil

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Cortex-M0+ Peripherals4.4 System timer, SysTickWhen enabled, the system timer counts down from the reload value to zero, reloads (wraps to)the value in the SYST_RVR on the next clock cycle, then decrements on subsequent clockcycles. Writing a value of zero to the SYST_RVR disables the counter on the next wrap. Whenthe counter transitions to zero, the COUNTFLAG status bit is set to 1. Reading SYST_CSRclears the COUNTFLAG bit to 0.Writing to the SYST_CVR clears the register and theCOUNTFLAG status bit to 0. The write does not trigger the SysTick exception logic. Readingthe register returns its value at the time it is accessed.NoteWhen the processor is halted for debugging the counter does not decrement.The system timer registers are:Table 4-19 System timer registers summaryAddress Name TypeRequiredprivilegeReset valueDescription0xE000E010 SYST_CSR RW Privileged 0x00000000 SysTick Control and Status Register0xE000E014 SYST_RVR RW Privileged Unknown SysTick Reload Value Register on page 4-170xE000E018 SYST_CVR RW Privileged Unknown SysTick Current Value Register on page 4-180xE000E01C SYST_CALIB RO Privileged IMPLEMENTATIONDEFINED a SysTick Calibration Value Register on page 4-18a. SysTick calibration value.4.4.1 SysTick Control and Status RegisterThe SYST_CSR enables the SysTick features. See the register summary in Table 4-19 for itsattributes. The bit assignments are:31 17 16 15 3 2 1 0ReservedReserved 0 00COUNTFLAGCLKSOURCETICKINTENABLETable 4-20 SYST_CSR bit assignmentsBits Name Function[31:17] - Reserved[16] COUNTFLAG Returns 1 if timer counted to 0 since the last read of this register[15:3] - ReservedARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 4-16ID041812Non-Confidential
Cortex-M0+ PeripheralsTable 4-20 SYST_CSR bit assignments (continued)Bits Name Function[2] CLKSOURCE Selects the SysTick timer clock source:0 = external reference clock1 = processor clock.[1] TICKINT Enables SysTick exception request:0 = counting down to zero does not assert the SysTick exception request1 = counting down to zero asserts the SysTick exception request.[0] ENABLE Enables the counter:0 = counter disabled1 = counter enabled.4.4.2 SysTick Reload Value RegisterThe SYST_RVR specifies the start value to load into the SYST_CVR. See the register summaryin Table 4-19 on page 4-16 for its attributes. The bit assignmentsare:31 24 230ReservedRELOADTable 4-21 SYST_RVR bit assignmentsBits Name Function[31:24] - Reserved[23:0] RELOAD Value to load into the SYST_CVR when the counter is enabled and when it reaches 0, see Calculating theRELOAD valueCalculating the RELOAD valueThe RELOAD value can be any value in the range 0x00000001-0x00FFFFFF. You can program avalue of 0, but this has no effect because the SysTick exception request and COUNTFLAG areactivated when counting from 1 to 0.To generate a multi-shot timer with a period of N processor clock cycles, use a RELOAD valueof N-1. For example, if the SysTick interrupt is required every 100 clock pulses, set RELOADto 99.ARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 4-17ID041812Non-Confidential
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Cortex-M0+ DevicesGeneric User Guid
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ContentsCortex-M0+ Devices Generic
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PrefaceTypographical ConventionsThe
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Chapter 1IntroductionThis chapter i
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IntroductionThe tight integration o
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Chapter 2The Cortex-M0+ ProcessorTh
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The Cortex-M0+ ProcessorIn Thread m
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The Cortex-M0+ ProcessorAccess thes
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The Cortex-M0+ ProcessorInterruptib
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The Cortex-M0+ Processor2.1.5 Data
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The Cortex-M0+ ProcessorThe differe
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The Cortex-M0+ ProcessorTable 2-10
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The Cortex-M0+ ProcessorLittle-endi
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The Cortex-M0+ ProcessorSysTickInte
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The Cortex-M0+ ProcessorIf software
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The Cortex-M0+ ProcessorThe process
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The Cortex-M0+ Processor2.5 Power m
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Chapter 3The Cortex-M0+ Instruction
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The Cortex-M0+ Instruction SetTable
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The Cortex-M0+ Instruction Set3.2 I
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The Cortex-M0+ Instruction SetNote
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The Cortex-M0+ Instruction Set3.3.5
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The Cortex-M0+ Instruction Set3.4 M
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Cortex-M0+ Devices Generic User Guide - Keil

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