Cortex-M0+ Devices Generic User Guide - Keil

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The Cortex-M0+ Instruction Set3.5.3 ASR, LSL, LSR, and RORArithmetic Shift Right, Logical Shift Left, Logical Shift Right, and Rotate Right.SyntaxASRS {Rd,} Rm, RsASRS {Rd,} Rm, #immLSLS {Rd,} Rm, RsLSLS {Rd,} Rm, #immLSRS {Rd,} Rm, RsLSRS {Rd,} Rm, #immRORS {Rd,} Rm, Rswhere:RdRmRsimmIs the destination register. If Rd is omitted, it is assumed to take the same value asRm.Is the register holding the value to be shifted.Is the register holding the shift length to apply to the value in Rm.Is the shift length. The range of shift length depends on the instruction:ASR shift length from 1 to 32LSL shift length from 0 to 31LSR shift length from 1 to 32.NoteMOVS Rd, Rm is a pseudonym for LSLS Rd, Rm, #0.OperationASR, LSL, LSR, and ROR perform an arithmetic-shift-left, logical-shift-left, logical-shift-right or aright-rotation of the bits in the register Rm by the number of places specified by the immediateimm or the value in the least-significant byte of the register specified by Rs.For details of what result is generated by the different instructions, see Shift operations onpage 3-6.RestrictionsIn these instructions, Rd, Rm, and Rs must only specify R0-R7. For non-immediate instructions,Rd and Rm must specify the same register.Condition flagsThese instructions update the N and Z flags according to the result.The C flag is updated to the last bit shifted out, except when the shift length is 0, see Shiftoperations on page 3-6. The V flag is left unmodified.ARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 3-24ID041812Non-Confidential
The Cortex-M0+ Instruction SetExamplesASRS R7, R5, #9 ; Arithmetic shift right by 9 bitsLSLS R1, R2, #3 ; Logical shift left by 3 bits with flag updateLSRS R4, R5, #6 ; Logical shift right by 6 bitsRORS R4, R4, R6 ; Rotate right by the value in the bottom byte of R6.ARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 3-25ID041812Non-Confidential
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Cortex-M0+ DevicesGeneric User Guid
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ContentsCortex-M0+ Devices Generic
Page 7 and 8:
PrefaceTypographical ConventionsThe
Page 9 and 10: Chapter 1IntroductionThis chapter i
Page 11 and 12: IntroductionThe tight integration o
Page 13 and 14: Chapter 2The Cortex-M0+ ProcessorTh
Page 15 and 16: The Cortex-M0+ ProcessorIn Thread m
Page 17 and 18: The Cortex-M0+ ProcessorAccess thes
Page 19 and 20: The Cortex-M0+ ProcessorInterruptib
Page 21 and 22: The Cortex-M0+ Processor2.1.5 Data
Page 23 and 24: The Cortex-M0+ ProcessorThe differe
Page 25 and 26: The Cortex-M0+ ProcessorTable 2-10
Page 27 and 28: The Cortex-M0+ ProcessorLittle-endi
Page 29 and 30: The Cortex-M0+ ProcessorSysTickInte
Page 31 and 32: The Cortex-M0+ ProcessorIf software
Page 33 and 34: The Cortex-M0+ ProcessorThe process
Page 35 and 36: The Cortex-M0+ Processor2.5 Power m
Page 37 and 38: Chapter 3The Cortex-M0+ Instruction
Page 39 and 40: The Cortex-M0+ Instruction SetTable
Page 41 and 42: The Cortex-M0+ Instruction Set3.2 I
Page 43 and 44: The Cortex-M0+ Instruction SetNote
Page 45 and 46: The Cortex-M0+ Instruction Set3.3.5
Page 47 and 48: The Cortex-M0+ Instruction Set3.4 M
Page 53 and 54: The Cortex-M0+ Instruction SetExamp
Page 55 and 56: The Cortex-M0+ Instruction Set3.5 G
Page 57 and 58: The Cortex-M0+ Instruction SetRestr
Page 59: The Cortex-M0+ Instruction Set3.5.2
Page 69 and 70: The Cortex-M0+ Instruction Set3.6 B
Page 71 and 72: The Cortex-M0+ Instruction SetCondi
Page 85 and 86: Chapter 4Cortex-M0+ PeripheralsThe
Page 87 and 88: Cortex-M0+ Peripherals4.2 Nested Ve
Page 89 and 90: Cortex-M0+ PeripheralsThe bit assig
Page 91 and 92: Cortex-M0+ Peripherals4.2.7 NVIC us
Page 93 and 94: Cortex-M0+ PeripheralsBits Name Fun
Page 95 and 96: Cortex-M0+ PeripheralsTable 4-11 IC
Page 97 and 98: Cortex-M0+ PeripheralsTable 4-13 AI
Page 99 and 100: Cortex-M0+ PeripheralsSystem Handle
Page 101 and 102: Cortex-M0+ PeripheralsTable 4-20 SY
Page 103 and 104: Cortex-M0+ Peripherals4.5 Memory Pr
Page 105 and 106: Cortex-M0+ PeripheralsSee the regis
Page 107 and 108: Cortex-M0+ PeripheralsTable 4-29 MP
Page 109 and 110: Cortex-M0+ PeripheralsThe smallest
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Cortex-M0+ Peripheralsbit controls
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Cortex-M0+ Devices Generic User Guide - Keil

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