Cortex-M0+ Devices Generic User Guide - Keil

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Cortex-M0+ PeripheralsSee the register summary in Table 4-9 on page 4-8 for the ICSR attributes. The bit assignmentsare:31 30 29 28 27 26 25 24 23 22 21 18 1712 116 50ReservedVECTPENDINGReservedVECTACTIVEISRPENDINGReservedPENDSTCLR, if SysTick is implementedPENDSTSET, if SysTick is implementedPENDSVCLRPENDSVSETReservedNMIPENDSETTable 4-11 ICSR bit assignmentsBits Name Type Function[31] NMIPENDSET RW NMI set-pending bit.Write:0 = no effect1 = changes NMI exception state to pending.Read:0 = NMI exception is not pending1 = NMI exception is pending.Because NMI is the highest-priority exception, normally the processor enters the NMIexception handler as soon as it detects a write of 1 to this bit. Entering the handler then clearsthis bit to 0. This means a read of this bit by the NMI exception handler returns 1 only if theNMI signal is reasserted while the processor is executing that handler.[30:29] - - Reserved.[28] PENDSVSET RW PendSV set-pending bit.Write:0 = no effect1 = changes PendSV exception state to pending.Read:0 = PendSV exception is not pending1 = PendSV exception is pending.Writing 1 to this bit is the only way to set the PendSV exception state to pending.[27] PENDSVCLR WO PendSV clear-pending bit.Write:0 = no effect1 = removes the pending state from the PendSV exception.[26] PENDSTSET RW SysTick exception set-pending bit.Write:0 = no effect1 = changes SysTick exception state to pending.Read:0 = SysTick exception is not pending1 = SysTick exception is pending.[26] - - Reserved.ARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 4-10ID041812Non-Confidential
Cortex-M0+ PeripheralsTable 4-11 ICSR bit assignments (continued)Bits Name Type Function[25] PENDSTCLR WO SysTick exception clear-pending bit.Write:0 = no effect1 = removes the pending state from the SysTick exception.This bit is WO. On a register read its value is Unknown.[25] - - Reserved.[24:23] - - Reserved.[22] ISRPENDING RO Interrupt pending flag, excluding NMI and Faults:0 = interrupt not pending1 = interrupt pending.[21:18] - - Reserved.[17:12] VECTPENDING RO Indicates the exception number of the highest priority pending enabled exception:0 = no pending exceptionsNonzero = the exception number of the highest priority pending enabled exception.[11:6] - - Reserved.[5:0] VECTACTIVE a RO Contains the active exception number:0 = Thread modeNonzero = The exception number a of the currently active exception.NoteSubtract 16 from this value to obtain the CMSIS IRQ number that identifies thecorresponding bit in the Interrupt Clear-Enable, Set-Enable, Clear-Pending, Set-pending, andPriority Register, see Table 2-5 on page 2-6.a. This is the same value as IPSR bits[5:0], see Interrupt Program Status Register on page 2-6.When you write to the ICSR, the effect is Unpredictable if you:• write 1 to the PENDSVSET bit and write 1 to the PENDSVCLR bit• write 1 to the PENDSTSET bit and write 1 to the PENDSTCLR bit.4.3.4 Vector Table Offset RegisterIf implemented, the VTOR indicates the offset of the vector table base address from memoryaddress 0x00000000. See the register summary in Table 4-12 on page 4-12 for its attributes.ARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 4-11ID041812Non-Confidential
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Cortex-M0+ DevicesGeneric User Guid
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ContentsCortex-M0+ Devices Generic
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PrefaceTypographical ConventionsThe
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Chapter 1IntroductionThis chapter i
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IntroductionThe tight integration o
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Chapter 2The Cortex-M0+ ProcessorTh
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The Cortex-M0+ ProcessorIn Thread m
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The Cortex-M0+ ProcessorAccess thes
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The Cortex-M0+ ProcessorInterruptib
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The Cortex-M0+ Processor2.1.5 Data
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The Cortex-M0+ ProcessorThe differe
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The Cortex-M0+ ProcessorTable 2-10
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The Cortex-M0+ ProcessorLittle-endi
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The Cortex-M0+ ProcessorSysTickInte
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The Cortex-M0+ ProcessorIf software
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The Cortex-M0+ ProcessorThe process
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The Cortex-M0+ Processor2.5 Power m
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Chapter 3The Cortex-M0+ Instruction
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The Cortex-M0+ Instruction SetTable
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The Cortex-M0+ Instruction Set3.2 I
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Cortex-M0+ Devices Generic User Guide - Keil

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