Cortex-M0+ Devices Generic User Guide - Keil

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The Cortex-M0+ Instruction Set3.7.10 SVCSupervisor Call.SyntaxSVC #immwhere:imm Is an integer in the range 0-255.OperationThe SVC instruction causes the SVC exception.imm is ignored by the processor. If required, it can be retrieved by the exception handler todetermine what service is being requested.RestrictionsExecuting the SVC instruction, while the current execution priority level is greater than or equalto that of the SVCall handler, results in a fault being generated.Condition flagsThis instruction does not change the flags.ExamplesSVC#0x32 ; Supervisor Call (SVC handler can extract the immediate value; by locating it through EXC_RETURN to identify the correct stack; and thence the stacked PC)ARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 3-46ID041812Non-Confidential
The Cortex-M0+ Instruction Set3.7.11 WFEWait For Event.SyntaxWFEOperationIf the event register is 0, WFE suspends execution until one of the following events occurs:• an exception, unless masked by the exception mask registers or the current priority level• an exception enters the Pending state, if SEVONPEND in the System Control Register is set• a Debug Entry request, if debug is enabled• an event signaled by a peripheral or another processor in a multiprocessor system usingthe SEV instruction.If the event register is 1, WFE clears it to 0 and completes immediately.For more information see Power management on page 2-23.NoteWFE is intended for power saving only. When writing software assume that WFE might behave asNOP.RestrictionsThere are no restrictions.Condition flagsThis instruction does not change the flags.ExamplesWFE; Wait for eventARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 3-47ID041812Non-Confidential
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Cortex-M0+ DevicesGeneric User Guid
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ContentsCortex-M0+ Devices Generic
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PrefaceTypographical ConventionsThe
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Chapter 1IntroductionThis chapter i
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IntroductionThe tight integration o
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Chapter 2The Cortex-M0+ ProcessorTh
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The Cortex-M0+ ProcessorIn Thread m
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The Cortex-M0+ ProcessorAccess thes
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The Cortex-M0+ ProcessorInterruptib
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The Cortex-M0+ Processor2.1.5 Data
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The Cortex-M0+ ProcessorThe differe
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The Cortex-M0+ ProcessorTable 2-10
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The Cortex-M0+ ProcessorLittle-endi
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The Cortex-M0+ ProcessorSysTickInte
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Page 37 and 38: Chapter 3The Cortex-M0+ Instruction
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Cortex-M0+ Devices Generic User Guide - Keil

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