Cortex-M0+ Devices Generic User Guide - Keil

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The Cortex-M0+ Instruction Set3.5.7 REV, REV16, and REVSHReverse bytes.SyntaxREV Rd, RnREV16 Rd, RnREVSH Rd, Rnwhere:RdRnIs the destination register.Is the source register.OperationUse these instructions to change endianness of data:REVREV16REVSHconverts 32-bit big-endian data into little-endian data or 32-bit little-endian datainto big-endian data.converts two packed 16-bit big-endian data into little-endian data or two packed16-bit little-endian data into big-endian data.converts 16-bit signed big-endian data into 32-bit signed little-endian data or16-bit signed little-endian data into 32-bit signed big-endian data.RestrictionsIn these instructions, Rd, and Rn must only specify R0-R7.Condition flagsThese instructions do not change the flags.ExamplesREV R3, R7 ; Reverse byte order of value in R7 and write it to R3REV16 R0, R0 ; Reverse byte order of each 16-bit halfword in R0REVSH R0, R5 ; Reverse signed halfwordARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 3-30ID041812Non-Confidential
The Cortex-M0+ Instruction Set3.5.8 SXT and UXTSign extend and Zero extend.SyntaxSXTB Rd, RmSXTH Rd, RmUXTB Rd, RmUXTH Rd, Rmwhere:RdRmIs the destination register.Is the register holding the value to be extended.OperationThese instructions extract bits from the resulting value:• SXTB extracts bits[7:0] and sign extends to 32 bits• UXTB extracts bits[7:0] and zero extends to 32 bits• SXTH extracts bits[15:0] and sign extends to 32 bits• UXTH extracts bits[15:0] and zero extends to 32 bits.RestrictionsIn these instructions, Rd and Rm must only specify R0-R7.Condition flagsThese instructions do not affect the flags.ExamplesSXTH R4, R6 ; Obtain the lower halfword of the; value in R6 and then sign extend to; 32 bits and write the result to R4.UXTB R3, R1 ; Extract lowest byte of the value in R1 and zero; extend it, and write the result to R3ARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 3-31ID041812Non-Confidential
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Cortex-M0+ DevicesGeneric User Guid
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ContentsCortex-M0+ Devices Generic
Page 7 and 8:
PrefaceTypographical ConventionsThe
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Chapter 1IntroductionThis chapter i
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IntroductionThe tight integration o
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Chapter 2The Cortex-M0+ ProcessorTh
Page 15 and 16: The Cortex-M0+ ProcessorIn Thread m
Page 17 and 18: The Cortex-M0+ ProcessorAccess thes
Page 19 and 20: The Cortex-M0+ ProcessorInterruptib
Page 21 and 22: The Cortex-M0+ Processor2.1.5 Data
Page 23 and 24: The Cortex-M0+ ProcessorThe differe
Page 25 and 26: The Cortex-M0+ ProcessorTable 2-10
Page 27 and 28: The Cortex-M0+ ProcessorLittle-endi
Page 29 and 30: The Cortex-M0+ ProcessorSysTickInte
Page 31 and 32: The Cortex-M0+ ProcessorIf software
Page 33 and 34: The Cortex-M0+ ProcessorThe process
Page 35 and 36: The Cortex-M0+ Processor2.5 Power m
Page 37 and 38: Chapter 3The Cortex-M0+ Instruction
Page 39 and 40: The Cortex-M0+ Instruction SetTable
Page 41 and 42: The Cortex-M0+ Instruction Set3.2 I
Page 43 and 44: The Cortex-M0+ Instruction SetNote
Page 45 and 46: The Cortex-M0+ Instruction Set3.3.5
Page 47 and 48: The Cortex-M0+ Instruction Set3.4 M
Page 53 and 54: The Cortex-M0+ Instruction SetExamp
Page 55 and 56: The Cortex-M0+ Instruction Set3.5 G
Page 57 and 58: The Cortex-M0+ Instruction SetRestr
Page 61 and 62: The Cortex-M0+ Instruction SetExamp
Page 65: The Cortex-M0+ Instruction Set3.5.6
Page 69 and 70: The Cortex-M0+ Instruction Set3.6 B
Page 71 and 72: The Cortex-M0+ Instruction SetCondi
Page 85 and 86: Chapter 4Cortex-M0+ PeripheralsThe
Page 87 and 88: Cortex-M0+ Peripherals4.2 Nested Ve
Page 89 and 90: Cortex-M0+ PeripheralsThe bit assig
Page 91 and 92: Cortex-M0+ Peripherals4.2.7 NVIC us
Page 93 and 94: Cortex-M0+ PeripheralsBits Name Fun
Page 95 and 96: Cortex-M0+ PeripheralsTable 4-11 IC
Page 97 and 98: Cortex-M0+ PeripheralsTable 4-13 AI
Page 99 and 100: Cortex-M0+ PeripheralsSystem Handle
Page 101 and 102: Cortex-M0+ PeripheralsTable 4-20 SY
Page 103 and 104: Cortex-M0+ Peripherals4.5 Memory Pr
Page 105 and 106: Cortex-M0+ PeripheralsSee the regis
Page 107 and 108: Cortex-M0+ PeripheralsTable 4-29 MP
Page 109 and 110: Cortex-M0+ PeripheralsThe smallest
Page 111 and 112: Cortex-M0+ Peripheralsbit controls
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Cortex-M0+ Devices Generic User Guide - Keil

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