Cortex-M0+ Devices Generic User Guide - Keil

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The Cortex-M0+ Instruction Set3.7.12 WFIWait for Interrupt.SyntaxWFIOperationWFI suspends execution until one of the following events occurs:• an exception• an interrupt becomes pending that would preempt if PRIMASK.PM was clear• a Debug Entry request, regardless of whether debug is enabled.NoteWFI is intended for power saving only. When writing software assume that WFI might behave asa NOP operation.RestrictionsThere are no restrictions.Condition flagsThis instruction does not change the flags.ExamplesWFI ; Wait for interruptARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 3-48ID041812Non-Confidential
Chapter 4Cortex-M0+ PeripheralsThe following sections describe the ARM Cortex-M0+ core peripherals:• About the Cortex-M0+ peripherals on page 4-2• Nested Vectored Interrupt Controller on page 4-3• System Control Block on page 4-8• System timer, SysTick on page 4-16• Memory Protection Unit on page 4-19• Single-cycle I/O Port on page 4-28.ARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 4-1ID041812Non-Confidential
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Cortex-M0+ DevicesGeneric User Guid
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ContentsCortex-M0+ Devices Generic
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PrefaceTypographical ConventionsThe
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Chapter 1IntroductionThis chapter i
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IntroductionThe tight integration o
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Chapter 2The Cortex-M0+ ProcessorTh
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The Cortex-M0+ ProcessorIn Thread m
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The Cortex-M0+ ProcessorAccess thes
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The Cortex-M0+ ProcessorInterruptib
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The Cortex-M0+ Processor2.1.5 Data
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The Cortex-M0+ ProcessorThe differe
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The Cortex-M0+ ProcessorTable 2-10
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The Cortex-M0+ ProcessorLittle-endi
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The Cortex-M0+ ProcessorSysTickInte
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The Cortex-M0+ ProcessorIf software
Page 33 and 34: The Cortex-M0+ ProcessorThe process
Page 35 and 36: The Cortex-M0+ Processor2.5 Power m
Page 37 and 38: Chapter 3The Cortex-M0+ Instruction
Page 39 and 40: The Cortex-M0+ Instruction SetTable
Page 41 and 42: The Cortex-M0+ Instruction Set3.2 I
Page 43 and 44: The Cortex-M0+ Instruction SetNote
Page 45 and 46: The Cortex-M0+ Instruction Set3.3.5
Page 47 and 48: The Cortex-M0+ Instruction Set3.4 M
Page 53 and 54: The Cortex-M0+ Instruction SetExamp
Page 55 and 56: The Cortex-M0+ Instruction Set3.5 G
Page 57 and 58: The Cortex-M0+ Instruction SetRestr
Page 61 and 62: The Cortex-M0+ Instruction SetExamp
Page 69 and 70: The Cortex-M0+ Instruction Set3.6 B
Page 71 and 72: The Cortex-M0+ Instruction SetCondi
Page 83: The Cortex-M0+ Instruction Set3.7.1
Page 87 and 88: Cortex-M0+ Peripherals4.2 Nested Ve
Page 89 and 90: Cortex-M0+ PeripheralsThe bit assig
Page 91 and 92: Cortex-M0+ Peripherals4.2.7 NVIC us
Page 93 and 94: Cortex-M0+ PeripheralsBits Name Fun
Page 95 and 96: Cortex-M0+ PeripheralsTable 4-11 IC
Page 97 and 98: Cortex-M0+ PeripheralsTable 4-13 AI
Page 99 and 100: Cortex-M0+ PeripheralsSystem Handle
Page 101 and 102: Cortex-M0+ PeripheralsTable 4-20 SY
Page 103 and 104: Cortex-M0+ Peripherals4.5 Memory Pr
Page 105 and 106: Cortex-M0+ PeripheralsSee the regis
Page 107 and 108: Cortex-M0+ PeripheralsTable 4-29 MP
Page 109 and 110: Cortex-M0+ PeripheralsThe smallest
Page 111 and 112: Cortex-M0+ Peripheralsbit controls
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Cortex-M0+ Devices Generic User Guide - Keil

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