Cortex-M0+ Devices Generic User Guide - Keil

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Cortex-M0+ PeripheralsUnless HFNMIENA is set to 1, the MPU is not enabled when the processor is executing thehandler for an exception with priority -1 or -2. These priorities are only possible when handlinga HardFault or NMI exception. Setting the HFNMIENA bit to 1 enables the MPU whenoperating with these two priorities.4.5.3 MPU Region Number RegisterThe MPU_RNR selects which memory region is referenced by the MPU_RBAR andMPU_RASR registers. See the register summary in Table 4-25 on page 4-20 for its attributes.The bit assignments are:31 8 7 0ReservedREGIONTable 4-28 MPU_RNR bit assignmentsBits Name Function[31:8] - Reserved.[7:0] REGION Indicates the MPU region referenced by the MPU_RBAR and MPU_RASR registers.The MPU supports 8 memory regions, so the permitted values of this field are 0-7.Normally, you write the required region number to this register before accessing theMPU_RBAR or MPU_RASR. However you can change the region number by writing to theMPU_RBAR with the VALID bit set to 1, see MPU Region Base Address Register. This writeupdates the value of the REGION field.4.5.4 MPU Region Base Address RegisterThe MPU_RBAR defines the base address of the MPU region selected by the MPU_RNR, andcan update the value of the MPU_RNR. See the register summary in Table 4-25 on page 4-20for its attributes.Write MPU_RBAR with the VALID bit set to 1 to change the current region number and updatethe MPU_RNR. The bit assignments are:31 N N-1 5 4 3 0ADDRReservedREGIONVALIDARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 4-22ID041812Non-Confidential
Cortex-M0+ PeripheralsTable 4-29 MPU_RBAR bit assignmentsBits Name Function[31:N] ADDR Region base address field. The value of N depends on the region size.For more information, see The ADDR field.[(N-1):5] - Reserved.[4] VALID MPU Region Number valid bit:Write:0 = MPU_RNR not changed, and the processor:• updates the base address for the region specified in the MPU_RNR• ignores the value of the REGION field.1 = the processor:• updates the value of the MPU_RNR to the value of the REGION field• updates the base address for the region specified in the REGION field.Always reads as zero.[3:0] REGION MPU region field.For the behavior on writes, see the description of the VALID field.On reads, returns the current region number, as specified by the MPU_RNR.The ADDR fieldThe ADDR field is bits[31:N] of the MPU_RBAR. The region size, as specified by the SIZEfield in the MPU_RASR, defines the value of N:N = Log 2 (Region size in bytes),If the region size is configured to 4GB, in the MPU_RASR, there is no valid ADDR field. Inthis case, the region occupies the complete memory map, and the base address is 0x00000000.The base address must be aligned to the size of the region. For example, a 64KB region must bealigned on a multiple of 64KB, for example, at 0x00010000 or 0x00020000.4.5.5 MPU Region Attribute and Size RegisterThe MPU_RASR defines the region size and memory attributes of the MPU region specified bythe MPU_RNR, and enables that region and any subregions. See the register summary inTable 4-25 on page 4-20 for its attributes.MPU_RASR is accessible using word or halfword accesses:• the most significant halfword holds the region attributes• the least significant halfword holds the region size and the region and subregion enablebits.ARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 4-23ID041812Non-Confidential
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Cortex-M0+ DevicesGeneric User Guid
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ContentsCortex-M0+ Devices Generic
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PrefaceTypographical ConventionsThe
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Chapter 1IntroductionThis chapter i
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IntroductionThe tight integration o
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Chapter 2The Cortex-M0+ ProcessorTh
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The Cortex-M0+ ProcessorIn Thread m
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The Cortex-M0+ ProcessorAccess thes
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The Cortex-M0+ ProcessorInterruptib
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The Cortex-M0+ Processor2.1.5 Data
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The Cortex-M0+ ProcessorThe differe
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The Cortex-M0+ ProcessorTable 2-10
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The Cortex-M0+ ProcessorLittle-endi
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The Cortex-M0+ ProcessorSysTickInte
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The Cortex-M0+ ProcessorThe process
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The Cortex-M0+ Processor2.5 Power m
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Chapter 3The Cortex-M0+ Instruction
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The Cortex-M0+ Instruction SetTable
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Cortex-M0+ Devices Generic User Guide - Keil

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