Cortex-M0+ Devices Generic User Guide - Keil

The Cortex-M0+ ProcessorWakeup from WFI or sleep-on-exitNormally, the processor wakes up only when it detects an exception with sufficient priority tocause exception entry.Some embedded systems might have to execute system restore tasks after the processor wakesup, and before it executes an interrupt handler. To achieve this set the PRIMASK.PM bit to 1.If an interrupt arrives that is enabled and has a higher priority than current exception priority,the processor wakes up but does not execute the interrupt handler until the processor setsPRIMASK.PM to zero. For more information about PRIMASK, see Exception mask register onpage 2-7.Wakeup from WFEThe processor wakes up if:• it detects an exception with sufficient priority to cause exception entry• it detects an external event signal, see The external event input• in a multiprocessor system, another processor in the system executes a SEV instruction.In addition, if the SEVONPEND bit in the SCR is set to 1, any new pending interrupt triggersan event and wakes up the processor, even if the interrupt is disabled or has insufficient priorityto cause exception entry. For more information about the SCR, see System Control Register onpage 4-13.2.5.3 The optional Wakeup Interrupt ControllerYour device might include a Wakeup Interrupt Controller (WIC), an optional peripheral that candetect an interrupt and wake the processor from deep sleep mode. The WIC is enabled onlywhen the DEEPSLEEP bit in the SCR is set to 1, see System Control Register on page 4-13.The WIC is not programmable, and does not have any registers or user interface. It operatesentirely from hardware signals.When the WIC is enabled and the processor enters deep sleep mode, the power management unitin the system can power down most of the Cortex-M0+ processor. This has the side effect ofstopping the SysTick timer. When the WIC receives an interrupt, it takes a number of clockcycles to wake up the processor and restore its state, before it can process the interrupt. Thismeans interrupt latency is increased in deep sleep mode.2.5.4 The external event inputYour device might include an external event input signal, so that device peripherals can signalthe processor. Tie this signal LOW if it is not used.This signal can wake up the processor from WFE, or set the internal WFE event register to oneto indicate that the processor must not enter sleep mode on a later WFE instruction, see Wait forevent on page 2-23.2.5.5 Power management programming hintsISO/IEC C cannot directly generate the WFI, WFE, and SEV instructions. CMSIS provides thefollowing intrinsic functions for these instructions:void __WFE(void) // Wait for Eventvoid __WFI(void) // Wait for Interruptvoid __SEV(void) // Send EventARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 2-24ID041812Non-Confidential