Cortex-M0+ Devices Generic User Guide - Keil

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Cortex-M0+ PeripheralsThe bit assignments are:31 7 6 0TBLOFFReservedTable 4-12 VTOR bit assignmentsBits Name Function[31:7] TBLOFF Vector table base offset field. It contains bits[31:7] of the offset of the table base from the bottom of the memorymap.[6:0] - Reserved.NoteThe vector table base must always be aligned to at least the number of exception vectorsimplemented. To ensure this, the Cortex-M0+ processor implements bit[7] (the least significantbit of TBLOFF) as RAZ/WI.4.3.5 Application Interrupt and Reset Control RegisterThe AIRCR provides endian status for data accesses and reset control of the system. See theregister summary in Table 4-9 on page 4-8 and Table 4-13 for its attributes.To write to this register, you must write 0x05FA to the VECTKEY field, otherwise the processorignores the write.The bit assignments are:31 16 15 14 3 2 1 0On read: ReservedOn write: VECTKEYReservedBits Name Type FunctionENDIANESSSYSRESETREQVECTCLRACTIVE, reserved for debug useReservedTable 4-13 AIRCR bit assignments[31:16] Read: ReservedWrite: VECTKEYRWRegister key:Reads as UnknownOn writes, write 0x05FA to VECTKEY, otherwise the write is ignored.[15] ENDIANNESS RO Data endianness implemented:0 = little-endian1 = big-endian.[14:3] - - ReservedARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 4-12ID041812Non-Confidential
Cortex-M0+ PeripheralsTable 4-13 AIRCR bit assignments (continued)Bits Name Type Function[2] SYSRESETREQ WO System reset request:0 = no effect1 = requests a system level reset.This bit reads as 0.[1] VECTCLRACTIVE WO Reserved for debug use. This bit reads as 0. When writing to the register you must write0 to this bit, otherwise behavior is Unpredictable.[0] - - Reserved.4.3.6 System Control RegisterThe SCR controls features of entry to and exit from low power state. See the register summaryin Table 4-9 on page 4-8 for its attributes. The bit assignments are:31 5 4 3 2 1 0ReservedSEVONPENDReservedSLEEPDEEPSLEEPONEXITReservedTable 4-14 SCR bit assignmentsBits Name Function[31:5] - Reserved.[4] SEVONPEND Send Event on Pending bit:0 = only enabled interrupts or events can wake up the processor, disabled interrupts are excluded1 = enabled events and all interrupts, including disabled interrupts, can wakeup the processor.When an event or interrupt enters pending state, the event signal wakes up the processor from WFE. Ifthe processor is not waiting for an event, the event is registered and affects the next WFE.The processor also wakes up on execution of an SEV instruction or an external event.[3] - Reserved.[2] SLEEPDEEP Controls whether the processor uses sleep or deep sleep as its low power mode:0 = sleep1 = deep sleep.[1] SLEEPONEXIT Indicates sleep-on-exit when returning from Handler mode to Thread mode:0 = do not sleep when returning to Thread mode1 = enter sleep, or deep sleep, on return from an ISR to Thread mode.Setting this bit to 1 enables an interrupt driven application to avoid returning to an empty mainapplication.[0] - Reserved.ARM DUI 0662A Copyright © 2012 ARM. All rights reserved. 4-13ID041812Non-Confidential
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Cortex-M0+ DevicesGeneric User Guid
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ContentsCortex-M0+ Devices Generic
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PrefaceTypographical ConventionsThe
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Chapter 1IntroductionThis chapter i
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IntroductionThe tight integration o
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Chapter 2The Cortex-M0+ ProcessorTh
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The Cortex-M0+ ProcessorIn Thread m
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The Cortex-M0+ ProcessorAccess thes
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The Cortex-M0+ ProcessorInterruptib
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The Cortex-M0+ Processor2.1.5 Data
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The Cortex-M0+ ProcessorThe differe
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The Cortex-M0+ ProcessorTable 2-10
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The Cortex-M0+ ProcessorLittle-endi
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The Cortex-M0+ ProcessorSysTickInte
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The Cortex-M0+ ProcessorIf software
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The Cortex-M0+ ProcessorThe process
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The Cortex-M0+ Processor2.5 Power m
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Chapter 3The Cortex-M0+ Instruction
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The Cortex-M0+ Instruction SetTable
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The Cortex-M0+ Instruction Set3.2 I
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The Cortex-M0+ Instruction SetNote
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Cortex-M0+ Devices Generic User Guide - Keil

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