CSEM Scientific and Technical Report 2008

MICROELECTRONICS
Christian Enz
The research activities conducted in recent years by the
Microelectronics Division has evolved from the design of
circuit building blocks towards the design of very complex
systems integrated on a single chip. Those systems-on-chip
or SoCs embed many functionalities such as microcontroller,
digital signal processing (DSP), low-leakage memory, radio
frequency (RF) transceivers, vision sensor arrays,
power/energy management and sensor interfaces. They all
are designed for low-power consumption and low–voltage
operation, strengthening further the long time low–power and
low-voltage differentiator that have made CSEM IC design
activities to be known worldwide. Today, the SoCs developed
at CSEM have reached a level of complexity that would be
difficult to extend much further, due to the enormous design
effort required to develop in-house all the components
mentioned above, despite the reuse of a maximum of existing
circuit building blocks and assemble them into a SoC.
In addition to low-power, the overall system miniaturization is
also a target. The latter can be partly achieved by integrating
more and more functions into the same silicon die, taking
advantage of the scaling of CMOS technology following
Moore’s law. A complementary approach (often named “more
than Moore”), consists in pushing miniaturization even further
by integrating additional heterogeneous devices such as RF
passives, resonators and filters, silicon time basis and sensors
together with the SoC in an advanced system-in-package
(SiP). This is basically the strategy followed by the
Microelectronics Division in recent years.
The research activities are organized around four different
generic technology tracks: digital SoC, sensory information
processing, RF CMOS and wireless, RF and piezoelectric
components. The roadmap for all these tracks is progressively
converging towards three SoC platforms and one SiP platform:
• the processor platform based on the 32-bit icyflex
processor family,
• the vision sensor platform based on the icycam SoC,
• the wireless platform based on the icycom SoC, and
• the MEMS-based radio platform.
Both the icycam and icycom SoCs are designed around the
first generation of icyflex 32-bit processor (icyflex1), which
combines the functions of a microcontroller together with
some digital signal processing (DSP) capabilities. The 32-bit
dual-MAC icyflex1 is described in more detail on page 23.
For applications requiring intensive computation, the icyflex1
is not powerful enough. The icyflex is therefore evolving
towards the icyflex4 offering up to 36 multiply-and-accumulate
(MAC) units for very high levels of single instruction multiple
data (SIMD) parallelism. On the lower end, the icyflex2 is a
smaller 16/32-bit RISC processor without DSP capabilities,
fitting control-type of applications. All the icyflex processors
share the same software development tools, developed at
CSEM based on the GNU tool suite. The icyflex processor
family is presented in more detail on page 22.
The icycam SoC developed for the new generation vision
sensor platform consists in the combination of a QVGA (320
by 240) active pixel array, an icyflex1 and 128 kB of
embedded SRAM memory. It has been integrated in a
0.18 µm CMOS process. The successful integration of icycam
is a major step forward for the vision sensor activity. Indeed, it
allowed on one hand to migrate the former analog vision
sensor chip from 0.5 µm CMOS to 0.18 µm and on the other
hand to move towards a digital vision sensor principle, taking
advantage of technology scaling. More details on the icycam
SoC can be found on page 20.
The icycom SoC is a RF transceiver operating in the 868 MHz
SRD band and including an icyflex1, together with embedded
SRAM memory and a 10-bit analog-to-digital converter (ADC).
It also offers all the flexibility in terms of power/energy
management and handling of supply voltage sources. The
design of the icycom SoC started at the end of 2008 and
silicon will be available in 2009. It will constitute a major
milestone for the RF low-power wireless activity, offering a
full-featured wireless development platform.
The design of complex SoCs obviously raises the problem of
chip validation and test. A methodology for SoC validation has
been developed and is now part of the CSEM design and
production flow. It is discussed in more detail on page 26.
High-Q resonators have always been a key component for
low-power SiP devices, with BAW resonators at RF for
implementing sharp filters with low insertion loss and ultralow
phase noise oscillators, and with silicon (Si) MEMS at lower
frequency for time and frequency references. Both the BAW
and Si MEMS resonators developed at CSEM take advantage
of the aluminium-nitride (AlN) thin film piezo-electric
technology available at CSEM. The optimization of the
geometry of BAW resonators has been thoroughly
investigated and is discussed in detail on page 27. Whether
BAW or Si MEMS, their packaging remains a critical issue.
CSEM has investigated new approaches for vacuum
packaging of Si MEMS resonators with AlN piezoelectric
activation which are presented on page 28.
The later high-Q resonators are used in the miniaturized
2.4 GHz MEMS-based radio for low-power wireless sensor
networks (WSN) or wireless body area networks (WBAN). A
new radio architecture has been developed to circumvent the
limited frequency tuning range of the high-Q BAW oscillator,
while still taking advantage of its ultralow phase noise. More
details about this radio can be found on page 24.
With the advent of the icyflex family of processor, CSEM has
been able to develop the icycam platform and next year it will
be the icycom platform. Each of these platforms is sufficiently
generic to allow customers to develop the software and to
customize the SoC as an application specific integrated circuit
(ASIC) targeting their particular needs. This achievement
constitutes a major step into a new era hopefully offering new
business opportunities, despite the omnipresent crisis.
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