CSEM Scientific and Technical Report 2008

The icyflex ® Processor Family
C. Arm, A. Corbaz, J.-M. Masgonty, M. Morgan, V. Moser, J.-L. Nagel, P. Volet
CSEM has long been involved in the design of processors for low-power consumption solutions. After the recent successes of the Macgic DSP and
the icyflex1 mixed DSP/control processor, development has started to derive two new icyflex architectures with new power saving features.
The design of ultra-low power processors at CSEM started
with very simple processors for the Swiss watch industry in
the early 1980s. In the 1990s, the CoolRISC processor – an
8-bit reduced instruction set computing (RISC) microcontroller
core – successfully offered a low power consumption solution
for simple control-type applications. In 2005, the Macgic [ 1]
16-to-24 bit digital signal processor (DSP) with its high level of
parallelism (4 multiply-and-accumulate, MAC, units) reached
best in class levels of power consumption for DSP-type
applications (42 µW/MHz/MAC at 1 V in 180 nm technology).
Figure 1: The roadmap of the icyflex processor family
The icyflex1 [ 2] architecture was designed to offer a flexible
processor with both DSP and control-type capabilities. Part of
its DSP architecture is inspired from the Macgic DSP, and
new features were added specifically to support a C language
compiler. The icyflex1 is customizable to fit individual
applications better. Several parameters (e.g. bus widths) can
be set to optimize the amount of hardware which is integrated
on silicon for a specific product. The icyflex1 is configurable at
run-time to further optimize the performance of the processor.
The resulting design is a 32-bit RISC processor, with
optimizations for 16-bit processing, with very low levels of
power consumption (60 µW/MHz/MAC at 1 V in 180 nm
technology).
Two new derivatives of the icyflex architecture were specified
in 2008: the icyflex2 is a smaller 16/32-bit RISC processor,
and the icyflex4 has a scalable architecture for applications
requiring high levels of parallel computing with limited energy
consumption. Both processors share a longer data processing
pipeline thereby supporting higher clock rates and/or lower
power consumption. Both processors also have a reviewed
instruction set to further optimize the sequencing of instruction
fetches and executions.
When completed in 2009, the icyflex2 processor will offer
efficient 16- and 32-bit processing for control-type applications.
Having been stripped of its DSP functionality (down to a single
multiplier) and its hardware breakpoint engines, its area is
estimated at under 50% of that of the icyflex1. Its area is
further reduced by the optimized instruction set operating with
smaller program memories, which typically represent a
significant part of the on-chip area, thereby reducing cost.
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The icyflex4 processor will have an additional vector
processing unit with a customizable amount of processing
slices (up to 8) each housing 4 MAC units for a total of up to
36 MAC units for very high levels of single instruction multiple
data (SIMD) parallelism. The icyflex4 is planned to replace the
Macgic DSP by the end of 2009 (see Figure 1). It targets clock
rates 2 times faster and overall throughput up to 10 times
greater than those of the Macgic.
The software development tools developed at CSEM for the
icyflex family of processors are based on the GNU tool suite [3] .
It includes a world-class C compiler (gcc), an assembler and
other binary utilities, and a debugger (gdb). A cycle-accurate
instruction set simulator (ISS) was created both for the
verification of the design and to plug inside gdb to add a
simulation-only mode to the debugger's on-chip debug (OCD)
mode. All these tools were encapsulated in the Eclipse open
integrated design environment (IDE). Plugging support for the
icyflex processor family into an existing open source tool suite
is a good way of reusing a software technology which has
proven its quality through a very large user base worldwide.
These tools have even begun supporting advanced features
such as the parallel execution of instructions which is one of
the key features of the icyflex performance.
The icyboard platform (see Figure 2) completes the design kit.
The motherboard offers basic services (USB connectivity,
power management, I/O, ADC) for up to 3 daughter boards.
Typical daughter boards carry an icyflex-based system-onchip
(SoC) and application specific devices (e.g. EEPROM).
Figure 2: Photograph of the icyboard hardware development platform
The development tools which are provided for the icyflex
processor family are key to its success. The icyflex processor
family offers a comprehensive solution for applications ranging
from simpler microcontrollers to large number-crunchers. Its
respective architectures are optimized to run through these
applications with minimized energy consumption.
[1] C. Arm, et al., “Low-power Quad MAC 170 µW/MHz 1.0 V
Macgic DSP Core”, ESSCIRC Dig. Tech. Papers, 2006
[2] C. Arm, et al., “A Low-power 32-bit Dual MAC 120 µW/MHz 1.0V
icyflex1 DSP/MCU Core”, in this report, page 23
[3] C. Arm, et al., “Low-power 32-bit Dual-MAC 120 µW/MHz 1.0V
icyflex1 DSP/MCU”, IEEE JSSC July 2009