CSEM Scientific and Technical Report 2008

Design of RF Passives in 65 nm CMOS
M. Kucera, F. Pengg, A. Vouilloz, J. Chabloz, R. Caseiro, N. Scolari, C. Monneron
Continuous cost reductions have for years been among the prevailing driving factors in IC and RF Design. To meet the challenges of the latest
process technologies, which have impressive gate densities of up to 800’000 gates per square millimeter, it is becoming increasingly important to
reduce the size of passive devices. This article gives an insight how CSEM has leveraged its experience and know-how to meet customer
requirements in a 65 nm CMOS technology.
Gate density is among the key performance indicators in ultra
deep-submicron CMOS technologies. Process technology
advancements have provided the digital design community
with impressive capabilities, almost doubling every 18 months
the number of digital logic gates per square millimeter.
Compared to digital design, constraints and requirements are
very different for RF circuits: gate density is not a concern, but
rather the size and quality of the RF blocks – generally
determined by the RF passive devices – for a given
performance. A major challenge in RF design is to optimise
the design of integrated passive devices like inductors and
capacitors. For highly integrated RF transceivers requiring
high performance or ultra low-power consumption, these
integrated passive devices are of utmost importance as their
achievable characteristics and quality factors will directly
determine the radio performance. Realizing innovative CMOS
radios [1] requires a thorough understanding of the achievable
and limiting characteristics of integrated RF passive devices. It
is thus essential to understand the device physics, to be
capable of measuring them using state-of-the art RF wafer
probers up to frequencies of typically 50 GHz, to extract the
device parameters and elaborate a simulation model that can
be used by the RF IC designers.
Silicon foundries generally propose a basic set of RF passive
devices in their design kits (DK), which can be used in generic
cases where current consumption, performance and size are
not an issue. The reasons are that universally usable and
suitable RF inductors do not exist: every inductor has its own
inductance value and self-resonance frequency due to its
parasitics. Furthermore as the silicon foundry knows neither
the operating frequency nor the required inductor value it can
only propose a limited usability of the required device or at
best some kind of scalable device. A further important
limitation lies in the fact that the associated models are often
only approximate, and rarely correct at the desired frequency
or the available metal layers. This leads to inaccurate
simulations and unpredictable results and specifications. This
is furthermore aggravated by the fact that foundries frequently
only support inductors integrated with the expensive RF
options, something customers often want to avoid, and which
is against the trend of using pure digital processes for
complex SOCs.
For these reasons CSEM has designed dedicated inductors
and capacitors in a recent 65 nm process (Figure 1) with the
following specific requirements and characteristics:
• Use of the metallization option defined and chosen by the
customer based on cost and requirements of the SoC.
• Consequent design and use of fully differential inductors:
they offer, for magnetic reasons, much better quality
factors, at approximately half the area.
• Optimising the self-resonance frequency of the inductor to
fit the operating frequency of the RF circuit, thereby
improving the quality factor, and hence the RF
performance (for example phase noise, gain or selectivity).
This also leads to a reduced current consumption.
• Exploiting the knowledge and the requirements of the
surrounding circuit: the knowledge of current and voltage
swings at the inductor nodes allows improvement and
optimisation of the geometry of the inductors in terms of
path width (which can be made variable along the
windings), number of turns in each metal layer, as well as
number of metal layers used.
• Optimising the inductor geometries and metal layers used
in the given circuit and fitting the resulting parasitic
capacitance to the entire circuit. This can turn unwanted
parasitics into useful devices for some circuits or nodes.
• Maintaining the optimal physical layout while also taking
into account manufacturing constraints and rules of the
foundry, especially concerning the maximum path width.
• Improvements of the capacitors compared to the DK are
also possible: by exploiting all the available metal layers,
as well as a geometry adaptation, it was possible to
improve the capacitance density by more than 15%. For
the variable capacitances (varicaps), a modification of the
layout towards a fully differential structure has allowed to
increase the quality factor while fitting the device ideally to
the otherwise fully differential VCO.
In the next phase the designed inductors and capacitors will
be measured, characterized and modelled. With these models
it will be possible to obtain correct and meaningful simulation
results even in ultra-deep submicron technologies.
Figure 1: Integrated inductors in a 65 nm process
[1] V. Peiris, et al., “A 1V 433/868MHz 25kb/s–FSK 2kb/s–OOK RF
Transceiver SoC in Standard Digital 0.18 µm CMOS”, in Int.
Solid-State Circ. Conf. Dig. of Tech. Papers, Feb. 2005, 258–259
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