CSEM Scientific and Technical Report 2008

High-speed Imagers
P. Buchschacher, S. Neukom, S. Beer, Y. Zha, Y. Li, R. Cook, T. Baechler
This paper provides insight in the design and evaluation of column parallel readout architectures for high speed digital imagers in a 0.18 µm optical
CMOS process.
About 100 years ago, Lucien Bull invented the stereoscopic
spark-drum camera, which took pictures at up to 2’000 frames
per second (fps) and was the first machine to analyse the
wing-beats of insects successfully (Figure 1, left). Dr Bull
imprisoned the insect in a glass tube so that, when it flew out,
it lifted up a tiny flap at the exit. This automatically closed the
electrical circuit operating the camera shutter (in effect the
insect was photographing itself).
Figure 1: Left – Lucien Bull with his high-speed (2kfps) camera, Paris,
1904 (Photo: NMEM Science & Society); Right – modern digital highspeed
camera (courtesy AOS Technologies AG)
Electronic image sensors of today can be considered as “highspeed”
as soon as they exceed video rates. The “speed”
(maximum frame rate) of an image sensor is indeed closely
related to its spatial resolution and more particularly to its
number of rows. For example, a sensor capable of 1’000 fps
while scanning 1’000 rows (row-rate = 1 µs) is able to deliver
10’000 fps when scanning a partial image of 100 rows (rowrate
=1 µs). The reason why the number of columns has
almost no impact on the sensor frame rate is that the majority
of high-speed sensors nowadays use column parallel readout
circuitry. Up to the 1990’s, CCD- and early CIS [ 1] delivered
analog output and thus A/D conversion had to be performed in
separate ICs. With the advent in the late 1990s of the first onchip
column-parallel ADCs, the way was paved for
implementing high-speed / high resolution digital imagers.
When this project was started in 2006, a typical high-speed
1.3 Megapixel digital CIS as used in a modern camera
(Figure 1, right) delivered 500 fps at full resolution (row-rate
= 2 µs) and needed a companion FPGA to sequence its
operation [2] . The target therefore was to push the speed and
functionality of such a CIS at a similar performance level as
Bull’s 100 year old bench, namely to sustain 2 kfps at full
resolution (row-rate = 0.5 µs) while integrating useful trigger
supporting functions (a modern ersatz of Bull’s glass-tube flap)
and auto-exposure controller on the same die.
In a first step, a partial integration of the sensor main analog
blocks in a 0.18 µm optical process with conventional
photodiodes (Figure 2) was realized. As the 12 µm2 pixel pitch
was requested from the application, well-known 5T snapshoot
pixels [1, 2] for the sensor array were selected. To
increase the column processing throughput, CSEM opted for a
two-row-at-a-time / time-interleaved row-addressing scheme.
For the readout circuitry an early low-power architecture [ 3]
which was boosted-up for high-speed operation was re-used.
34
4mm
3mm
Figure 2: 1 st integration of the analog blocks. Left – test bed;
Right – IC.
The readout was made of data-difference sampling (DDS)
stages with programmable gain and 10-bit SAR ADCs running
at four times the row-rate (125 ns / column), as depicted in
Figure 3 left. The evaluation of this 1st integration showed
mixed results: on the one hand, the optical characterisation of
the pixel diodes as well as the functionality of the ADCs was
successful, but on the other hand the DDS stages did not
work properly.
CSEM thus devised a redesign of the readout path, in which
the throughput of the analog blocks to one time the row-rate
(500 ns/column, Figure 3 center) was essentially reduced.
This 2nd chip, which is now in the process of being integrated,
incorporates the full digital functionality of the target 1.3 Mpix
sensor (on-chip sequencer, ROI trigger, exposure controller),
as well as (new) pinned photodiodes for improved sensitivity.
2
8*10
Top readout
Pixel array
DDS DDS
DDS
1
Bottom
readout
1
Bottom
readout
ADC ADC
ADC
10
10
Mux Mux
8*10
8*10
2
DDS
DDS
DDS
DDS
ADC
ADC
ADC
ADC
8*10
Top readout
Pixel array
DDS
DDS
ADC
ADC
10mm
5mm
Figure 3: Left – 1 st readout architecture; Center – 2 nd readout
architecture; Right – 2 nd integration with 256x256 pixel field
This work was partly funded by the CTI/KTI (contract number
8035.2 NMPP-NM). CSEM thanks them for their support.
[1] S. Lauxtermann, et al., “A high speed CMOS imager acquiring
5000 frames/sec”, dig. IEDM '99 conf, pp.875-878, December
1999
[2] A. Krymski, et al., “A High Speed, 500 fps, 1024x1024 CMOS
Active Pixel Sensor”, IEEE VLSI Cir. conf., June 1999, 137-138
[3] M. Ansorge, et al., “Smart Low-Power CMOS Cameras for 3G
Mobile Communicators”, proc. IEEE ICSC'02, June 2002, 216-
225