CSEM Scientific and Technical Report 2008

Packaging Technology for Silicon Resonators
J. Baborowski, A. Pezous, C. Muller, G. Spinola Durante, M.-A. Dubois
Recently, two types of Low Frequency silicon resonators with AlN piezoelectric activation have been developed. Whatever the type of resonator, its
properties are enhanced when operated under vacuum. The main motivation for the packaging of resonator under vacuum is to increase the
Q factor, and to guarantee a long-term stability for frequency reference. In order to minimize the size of packaged resonators, wafer level packaging
(WLP) is the right option. WLP also offers other opportunities for further integration of RF MEMS and IC components.
Hermetic packaging at low pressure is one of the largest
barriers to commercialisation of MEMS timing reference. In
this project the solutions for WLP of the resonator have been
demonstrated.
Packaging of resonators consists in building a hermetic cavity
around the resonator. This is done in three steps (Figure 1):
1. Fabrication of the AlN/Si resonator
2. Wafer-to-Wafer rear side packaging
3. Die-to-die front-side packaging performed under vacuum.
Figure 1: Schematic view of packaging principle for AlN/Si resonators
For rear side packaging, two approaches were tested. The
first solution consists in the fabrication of buried cavities within
the SOI wafer, followed by the building of the piezoelectric
resonator directly on the membrane. The second solution
uses a capping wafer (thin silicon or Pyrex) sealed by low
temperature fusion bonding or by anodic bonding. Both
bonding methods require an extremely smooth and
residue-free surface of the wafer. Hermetic sealing with high
shear strength was obtained for resonator/Pyrex sandwich.
Metallic alloy materials can provide low-permeability sealing
characteristics. The resonator/Pyrex chips are vacuum
encapsulated using silicon caps and AuSn (80% wt Au)
soldering technology. A metallization layer (TiW-Au) is
deposited and patterned (lift-off) on the resonator wafer. On
the capping wafer the AuSn electroplating process was
carried out at the Fraunhofer Institute for Reliability and
Microintegration (IZM FhG) and the final sealing process at
CSEM Alpnach. The quality of the sealing resulting in vacuum
level in the cavity is monitored through measurements of
resonator Q factor. In this version, the electrical contact with
the resonator is established via metal lines crossing the
sealing ring. The electrical signal and metal sealing ring are
isolated by an adequate passivation layer (SiO2 or SiON).
1 MHz extensional mode resonators (Figure 2) have been
packaged using thin Si capping (200 μm, Figure 3) and Pyrex
wafer (300 μm). The total size of the packaged resonator is
28
3
1
2
top cap
resonator
bottom cap
4x3x1 mm 3 . Further miniaturization can be achieved with 32 to
120 kHz flexural resonators (2x2x0.6 mm 3 ) using the same
technology. In a previous project the effect of air pressure has
been demonstrated showing that in order to obtain stable
values of Q factors higher than 100000 it is mandatory to
maintain the resonator at a pressure below 1 mbar [ 1] .
Packaged resonators exhibit a Q factor in vacuum as high as
140000, a coupling factor k 2 eff of 0.06%, a motional resistance
below 200 Ohm and a mainly linear TCf of -28.5 ppm/°C.
Electronic compensation of this thermal drift has been
demonstrated in the MIP Packtime [2] . The integration of WLP
resonator, BAW filters and IC to build a miniaturized ULP
MEMS radio is the scope of the EU IP “MINAmI” [3] .
Figure 2: Top view of 1MHz AlN/Si resonators with sealing ring
Figure 3: Top view of capping die with sealing ring
[1] J. Baborowski, et al., “Silicon Resonators: Thermal
Compensation and Q Factor Optimization”, CSEM Scientific
Report 2007, page 9
[2] D. Ruffieux, et al., “PackTime: Zero-Level Packaging of Silicon
Time-base for RTC and Reference Frequency Applications”, in
this report, page 10
[3] http://www.fp6-minami.org