Atmel AT89C51ID2 Data Sheet - Keil

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102 AT89C51ID2 Figure 39. Full-Duplex Master-Slave Interconnection SPI Clock Generator 8-bit Shift register Master MCU 8-bit Shift register Master mode The SPI operates in Master mode when the Master bit, MSTR (1) , in the SPCON register is set. Only one Master SPI device can initiate transmissions. Software begins the transmission from a Master SPI module by writing to the Serial Peripheral Data Register (SPDAT). If the shift register is empty, the byte is immediately transferred to the shift register. The byte begins shifting out on MOSI pin under the control of the serial clock, SCK. Simultaneously, another byte shifts in from the Slave on the Master’s MISO pin. The transmission ends when the Serial Peripheral transfer data flag, SPIF, in SPSTA becomes set. At the same time that SPIF becomes set, the received byte from the Slave is transferred to the receive data register in SPDAT. Software clears SPIF by reading the Serial Peripheral Status register (SPSTA) with the SPIF bit set, and then reading the SPDAT. Slave mode The SPI operates in Slave mode when the Master bit, MSTR (2) , in the SPCON register is cleared. Before a data transmission occurs, the Slave Select pin, SS, of the Slave device must be set to’0’. SS must remain low until the transmission is complete. In a Slave SPI module, data enters the shift register under the control of the SCK from the Master SPI module. After a byte enters the shift register, it is immediately transferred to the receive data register in SPDAT, and the SPIF bit is set. To prevent an overflow condition, Slave software must then read the SPDAT before another byte enters the shift register (3) . A Slave SPI must complete the write to the SPDAT (shift register) at least one bus cycle before the Master SPI starts a transmission. If the write to the data register is late, the SPI transmits the data already in the shift register from the previous transmission. Transmission Formats Software can select any of four combinations of serial clock (SCK) phase and polarity using two bits in the SPCON: the Clock POLarity (CPOL (4) ) and the Clock PHAse (CPHA 4 ). CPOL defines the default SCK line level in idle state. It has no significant effect on the transmission format. CPHA defines the edges on which the input data are sampled and the edges on which the output data are shifted (Figure 40 and Figure 41). The clock phase and polarity should be identical for the Master SPI device and the communicating Slave device. MISO MOSI MISO MOSI SCK SCK SS VDD SS VSS Slave MCU 1. The SPI module should be configured as a Master before it is enabled (SPEN set). Also the Master SPI should be configured before the Slave SPI. 2. The SPI module should be configured as a Slave before it is enabled (SPEN set). 3. The maximum frequency of the SCK for an SPI configured as a Slave is the bus clock speed. 4. Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN =’0’). 4289A–8051–09/03
Figure 40. Data Transmission Format (CPHA = 0) 4289A–8051–09/03 SCK cycle number SPEN (internal) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from Master) MISO (from Slave) SS (to Slave) Capture point Figure 41. Data Transmission Format (CPHA = 1) SCK cycle number SPEN (internal) SCK (CPOL = 0) SCK (CPOL = 1) MOSI (from Master) MISO (from Slave) SS (to Slave) Capture point Figure 42. CPHA/SS Timing MISO/MOSI Master SS Slave SS (CPHA = 0) Slave SS (CPHA = 1) 1 2 3 4 5 6 7 8 MSB bit6 bit5 bit4 bit3 bit2 bit1 LSB MSB bit6 bit5 bit4 bit3 bit2 bit1 LSB 1 2 3 4 5 6 7 8 MSB bit6 bit5 bit4 bit3 bit2 bit1 LSB MSB bit6 bit5 bit4 bit3 bit2 bit1 LSB Byte 1 Byte 2 Byte 3 AT89C51ID2 As shown in Figure 40, the first SCK edge is the MSB capture strobe. Therefore the Slave must begin driving its data before the first SCK edge, and a falling edge on the SS pin is used to start the transmission. The SS pin must be toggled high and then low between each byte transmitted (Figure 42). Figure 41 shows an SPI transmission in which CPHA is’1’. In this case, the Master begins driving its MOSI pin on the first SCK edge. Therefore the Slave uses the first SCK edge as a start transmission signal. The SS pin can remain low between transmissions (Figure 42). This format may be preffered in systems having only one Master and only one Slave driving the MISO data line. 103
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Features 80C52 Compatible - 8051 In
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Block Diagram Figure 1. Block Diagr
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Table 2. C51 Core SFRs 4289A-8051-0
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Table 8. PCA SFRs 4289A-8051-09/03
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Table 13. SFR Mapping F8h F0h E8h E
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11 AT89C51ID2 4289A-8051-09/03 50 4
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Table 14. Pin Description (Continue
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Oscillators 4289A-8051-09/03 AT89C5
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4289A-8051-09/03 Table 18. PCON Reg
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4289A-8051-09/03 AT89C51ID2 It is a
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4289A-8051-09/03 - FCLK CPU and FCL
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Figure 5. Mode Switching Waveforms
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4289A-8051-09/03 Table 21. CKCON1 R
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4289A-8051-09/03 Table 22. AUXR1 re
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Expanded RAM (XRAM) Figure 7. Inter
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Registers Table 23. AUXR Register A
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Reset Output 4289A-8051-09/03 AT89C
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Figure 12. Power Fail Detect Vcc 42
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Programmable Clock- Output 4289A-80
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Registers Table 24. T2CON Register
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Programmable Counter Array PCA 4289
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4289A-8051-09/03 Table 26. CMOD Reg
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Figure 16. PCA Interrupt System 428
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4289A-8051-09/03 Table 29. PCA Modu
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4289A-8051-09/03 AT89C51ID2 PCA Cap
Page 51 and 52: Figure 19. PCA High Speed Output Mo
Page 53 and 54: 4289A-8051-09/03 AT89C51ID2 Serial
Page 55 and 56: 4289A-8051-09/03 AT89C51ID2 The SAD
Page 57 and 58: Internal Baud Rate Generator (BRG)
Page 59 and 60: UART Registers Table 40. SADEN Regi
Page 61 and 62: 4289A-8051-09/03 Table 44. T2CON Re
Page 63 and 64: 4289A-8051-09/03 Table 46. BDRCON R
Page 65 and 66: 4289A-8051-09/03 AT89C51ID2 Registe
Page 67 and 68: 4289A-8051-09/03 Table 49. IPL0 Reg
Page 69 and 70: 4289A-8051-09/03 Table 51. IEN1 Reg
Page 71 and 72: 4289A-8051-09/03 Table 54. IPH1 Reg
Page 73 and 74: Power Management 4289A-8051-09/03 A
Page 75 and 76: 4289A-8051-09/03 AT89C51ID2 pins, t
Page 77 and 78: AT89C51ID2 Keyboard Interface The A
Page 79 and 80: 4289A-8051-09/03 Table 59. KBE Regi
Page 81 and 82: 4289A-8051-09/03 AT89C51ID2 2-wire
Page 83 and 84: 4289A-8051-09/03 AT89C51ID2 Descrip
Page 85 and 86: 4289A-8051-09/03 AT89C51ID2 When th
Page 87 and 88: Figure 33. Format and State in the
Page 93 and 94: Table 67. Status in Slave Receiver
Page 95 and 96: Table 68. Status in Slave Transmitt
Page 97 and 98: 4289A-8051-09/03 Bit Number 1 SD1 A
Page 99 and 100: Serial Port Interface (SPI) 4289A-8
Page 101: Functional Description Figure 38 sh
Page 105 and 106: 4289A-8051-09/03 Figure 43. SPI Int
Page 107 and 108: Serial Peripheral DATa register (SP
Page 109 and 110: WDT During Power Down and Idle 4289
Page 111 and 112: 4289A-8051-09/03 AT89C51ID2 Power-o
Page 113 and 114: 4289A-8051-09/03 Figure 44. Recomme
Page 115 and 116: Registers Table 85. EECON Register
Page 117 and 118: 4289A-8051-09/03 AT89C51ID2 Flash M
Page 119 and 120: 4289A-8051-09/03 Table 88. Program
Page 121 and 122: 4289A-8051-09/03 Table 92. Program
Page 123 and 124: Functional Description Figure 48. B
Page 125 and 126: Boot Process Figure 49. Bootloader
Page 127 and 128: Functional Description 4289A-8051-0
Page 129 and 130: Flow Description 4289A-8051-09/03 A
Page 131 and 132: Write / Program Commands This flow
Page 133 and 134: Display Data Description Figure 55.
Page 135 and 136: Example 4289A-8051-09/03 Read funct
Page 137 and 138: 4289A-8051-09/03 Table 95. ISP Comm
Page 139 and 140: Table 96. API Call Summary (Continu
Page 141 and 142: T A = -40°C to +85°C; V SS = 0V;
Page 143 and 144: External Program Memory Characteris
Page 145 and 146: External Program Memory Read Cycle
Page 147 and 148: External Data Memory Write Cycle 42
Page 149 and 150: AC Testing Input/Output Waveforms F
Page 151 and 152: Ordering Information 4289A-8051-09/
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VQFP44 4289A-8051-09/03 AT89C51ID2
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PLCC68 4289A-8051-09/03 AT89C51ID2
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4289A-8051-09/03 AT89C51ID2 Pulse W
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Atmel Corporation Atmel Operations
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Atmel AT89C51ID2 Data Sheet - Keil

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