Atmel AT89C51ID2 Data Sheet - Keil

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Bootloader Architecture Introduction The bootloader manages a communication according to a specific defined protocol to provide the whole access and service on Flash memory. Furthermore, all accesses and routines can be called from the user application. access via specific protocol access from user application 122 <strong>AT89C51ID2</strong> Figure 47. Diagram Context Description Bootloader Acronyms ISP : In-System Programming SBV: Software Boot Vector BSB: Boot Status Byte SSB: Software Security Bit HW : Hardware Byte Flash memory 4289A–8051–09/03
Functional Description Figure 48. Bootloader Functional Description 4289A–8051–09/03 Exernal host with Specific Protocol Communication ISP Communication Management Flash Memory Management Flash Memory User Call Management (API ) <strong>AT89C51ID2</strong> User Application On the above diagram, the on chip bootloader processes are: ISP Communication Management The purpose of this process is to manage the communication and its protocol between the on-chip bootloader and a external device. The on-chip ROM implement a serial protocol (see section Bootloader Protocol). This process translate serial communication frame (UART) into flash memory acess (read, write, erase ...). User Call Management Several Application Program Interface (API) calls are available for use by an application program to permit selective erasing and programming of Flash pages. All calls are made through a common interface (API calls), included in the ROM bootloader. The programming functions are selected by setting up the microcontroller’s registers before making a call to a common entry point (0xFFF0). Results are returned in the registers. The purpose on this process is to translate the registers values into internal Flash Memory Management. Flash Memory Management This process manages low level access to flash memory (performs read and write access). 123
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Features 80C52 Compatible - 8051 In
Page 3 and 4:
Block Diagram Figure 1. Block Diagr
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Table 2. C51 Core SFRs 4289A-8051-0
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Table 8. PCA SFRs 4289A-8051-09/03
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Table 13. SFR Mapping F8h F0h E8h E
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11 AT89C51ID2 4289A-8051-09/03 50 4
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Table 14. Pin Description (Continue
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Oscillators 4289A-8051-09/03 AT89C5
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4289A-8051-09/03 Table 18. PCON Reg
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4289A-8051-09/03 AT89C51ID2 It is a
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4289A-8051-09/03 - FCLK CPU and FCL
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Figure 5. Mode Switching Waveforms
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4289A-8051-09/03 Table 21. CKCON1 R
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4289A-8051-09/03 Table 22. AUXR1 re
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Expanded RAM (XRAM) Figure 7. Inter
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Registers Table 23. AUXR Register A
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Reset Output 4289A-8051-09/03 AT89C
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Figure 12. Power Fail Detect Vcc 42
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Programmable Clock- Output 4289A-80
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Registers Table 24. T2CON Register
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Programmable Counter Array PCA 4289
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4289A-8051-09/03 Table 26. CMOD Reg
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Figure 16. PCA Interrupt System 428
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4289A-8051-09/03 Table 29. PCA Modu
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4289A-8051-09/03 AT89C51ID2 PCA Cap
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Figure 19. PCA High Speed Output Mo
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4289A-8051-09/03 AT89C51ID2 Serial
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4289A-8051-09/03 AT89C51ID2 The SAD
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Internal Baud Rate Generator (BRG)
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UART Registers Table 40. SADEN Regi
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4289A-8051-09/03 Table 44. T2CON Re
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4289A-8051-09/03 Table 46. BDRCON R
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4289A-8051-09/03 AT89C51ID2 Registe
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4289A-8051-09/03 Table 49. IPL0 Reg
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4289A-8051-09/03 Table 51. IEN1 Reg
Page 71 and 72: 4289A-8051-09/03 Table 54. IPH1 Reg
Page 73 and 74: Power Management 4289A-8051-09/03 A
Page 75 and 76: 4289A-8051-09/03 AT89C51ID2 pins, t
Page 77 and 78: AT89C51ID2 Keyboard Interface The A
Page 79 and 80: 4289A-8051-09/03 Table 59. KBE Regi
Page 81 and 82: 4289A-8051-09/03 AT89C51ID2 2-wire
Page 83 and 84: 4289A-8051-09/03 AT89C51ID2 Descrip
Page 85 and 86: 4289A-8051-09/03 AT89C51ID2 When th
Page 87 and 88: Figure 33. Format and State in the
Page 93 and 94: Table 67. Status in Slave Receiver
Page 95 and 96: Table 68. Status in Slave Transmitt
Page 97 and 98: 4289A-8051-09/03 Bit Number 1 SD1 A
Page 99 and 100: Serial Port Interface (SPI) 4289A-8
Page 101 and 102: Functional Description Figure 38 sh
Page 103 and 104: Figure 40. Data Transmission Format
Page 105 and 106: 4289A-8051-09/03 Figure 43. SPI Int
Page 107 and 108: Serial Peripheral DATa register (SP
Page 109 and 110: WDT During Power Down and Idle 4289
Page 111 and 112: 4289A-8051-09/03 AT89C51ID2 Power-o
Page 113 and 114: 4289A-8051-09/03 Figure 44. Recomme
Page 115 and 116: Registers Table 85. EECON Register
Page 117 and 118: 4289A-8051-09/03 AT89C51ID2 Flash M
Page 119 and 120: 4289A-8051-09/03 Table 88. Program
Page 121: 4289A-8051-09/03 Table 92. Program
Page 125 and 126: Boot Process Figure 49. Bootloader
Page 127 and 128: Functional Description 4289A-8051-0
Page 129 and 130: Flow Description 4289A-8051-09/03 A
Page 131 and 132: Write / Program Commands This flow
Page 133 and 134: Display Data Description Figure 55.
Page 135 and 136: Example 4289A-8051-09/03 Read funct
Page 137 and 138: 4289A-8051-09/03 Table 95. ISP Comm
Page 139 and 140: Table 96. API Call Summary (Continu
Page 141 and 142: T A = -40°C to +85°C; V SS = 0V;
Page 143 and 144: External Program Memory Characteris
Page 145 and 146: External Program Memory Read Cycle
Page 147 and 148: External Data Memory Write Cycle 42
Page 149 and 150: AC Testing Input/Output Waveforms F
Page 151 and 152: Ordering Information 4289A-8051-09/
Page 153 and 154: VQFP44 4289A-8051-09/03 AT89C51ID2
Page 155 and 156: PLCC68 4289A-8051-09/03 AT89C51ID2
Page 157 and 158: 4289A-8051-09/03 AT89C51ID2 Pulse W
Page 159: Atmel Corporation Atmel Operations
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Atmel AT89C51ID2 Data Sheet - Keil

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