Atmel AT89C51ID2 Data Sheet - Keil

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16 <strong>AT89C51ID2</strong> Table 16. OSCCON Register OSCCON- Oscillator Control Register (86h) 7 6 5 4 3 2 1 0 - - - - - SCLKT0 OscBEn OscAEn Bit Number Bit Mnemonic Description 7 - Reserved 6 - Reserved 5 - Reserved 4 - Reserved 3 - Reserved 2 SCLKT0 1 OscBEn 0 OscAEn Reset Value = XXXX X0’HSB.OSC’’HSB.OSC’b (see Hardware Security Byte (HSB)) Not bit addressable Table 17. CKRL Register CKRL - Clock Reload Register Reset Value = 1111 1111b Not bit addressable Sub Clock Timer0 Cleared by software to select T0 pin Set by software to select T0 Sub Clock Cleared by hardware after a Power Up OscB enable bit Set by software to run OscB Cleared by software to stop OscB Programmed by hardware after a Power-up regarding HSB.OSC (Default cleared, OSCB stopped) OscA enable bit Set by software to run OscA Cleared by software to stop OscA Programmed by hardware after a Power-up regarding HSB.OSC(Default Set, OSCA runs) 7 6 5 4 3 2 1 0 - - - - - - - - Bit Number Mnemonic Description 7:0 CKRL Clock Reload Register: Prescaler value 4289A–8051–09/03
4289A–8051–09/03 Table 18. PCON Register PCON - Power Control Register (87h) Reset Value = 00X1 0000b Not bit addressable <strong>AT89C51ID2</strong> 7 6 5 4 3 2 1 0 SMOD1 SMOD0 - POF GF1 GF0 PD IDL Bit Number Bit Mnemonic Description 7 SMOD1 6 SMOD0 5 - 4 POF 3 GF1 2 GF0 1 PD 0 IDL Serial port Mode bit 1 Set to select double baud rate in mode 1, 2 or 3. Serial port Mode bit 0 Cleared to select SM0 bit in SCON register. Set to select FE bit in SCON register. Reserved The value read from this bit is indeterminate. Do not set this bit. Power-Off Flag Cleared to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software. General purpose Flag Cleared by software for general purpose usage. Set by software for general purpose usage. General purpose Flag Cleared by software for general purpose usage. Set by software for general purpose usage. Power-Down mode bit Cleared by hardware when reset occurs. Set to enter power-down mode. Idle mode bit Cleared by hardware when interrupt or reset occurs. Set to enter idle mode. 17
Page 1 and 2: Features 80C52 Compatible - 8051 In
Page 3 and 4: Block Diagram Figure 1. Block Diagr
Page 5 and 6: Table 2. C51 Core SFRs 4289A-8051-0
Page 7 and 8: Table 8. PCA SFRs 4289A-8051-09/03
Page 9 and 10: Table 13. SFR Mapping F8h F0h E8h E
Page 11 and 12: 11 AT89C51ID2 4289A-8051-09/03 50 4
Page 13 and 14: Table 14. Pin Description (Continue
Page 15: Oscillators 4289A-8051-09/03 AT89C5
Page 19 and 20: 4289A-8051-09/03 AT89C51ID2 It is a
Page 21 and 22: 4289A-8051-09/03 - FCLK CPU and FCL
Page 23 and 24: Figure 5. Mode Switching Waveforms
Page 25 and 26: 4289A-8051-09/03 Table 21. CKCON1 R
Page 27 and 28: 4289A-8051-09/03 Table 22. AUXR1 re
Page 29 and 30: Expanded RAM (XRAM) Figure 7. Inter
Page 31 and 32: Registers Table 23. AUXR Register A
Page 33 and 34: Reset Output 4289A-8051-09/03 AT89C
Page 35 and 36: Figure 12. Power Fail Detect Vcc 42
Page 37 and 38: Programmable Clock- Output 4289A-80
Page 39 and 40: Registers Table 24. T2CON Register
Page 41 and 42: Programmable Counter Array PCA 4289
Page 43 and 44: 4289A-8051-09/03 Table 26. CMOD Reg
Page 45 and 46: Figure 16. PCA Interrupt System 428
Page 47 and 48: 4289A-8051-09/03 Table 29. PCA Modu
Page 49 and 50: 4289A-8051-09/03 AT89C51ID2 PCA Cap
Page 51 and 52: Figure 19. PCA High Speed Output Mo
Page 53 and 54: 4289A-8051-09/03 AT89C51ID2 Serial
Page 55 and 56: 4289A-8051-09/03 AT89C51ID2 The SAD
Page 57 and 58: Internal Baud Rate Generator (BRG)
Page 59 and 60: UART Registers Table 40. SADEN Regi
Page 61 and 62: 4289A-8051-09/03 Table 44. T2CON Re
Page 63 and 64: 4289A-8051-09/03 Table 46. BDRCON R
Page 65 and 66: 4289A-8051-09/03 AT89C51ID2 Registe
Page 67 and 68:
4289A-8051-09/03 Table 49. IPL0 Reg
Page 69 and 70:
4289A-8051-09/03 Table 51. IEN1 Reg
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4289A-8051-09/03 Table 54. IPH1 Reg
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Power Management 4289A-8051-09/03 A
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4289A-8051-09/03 AT89C51ID2 pins, t
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AT89C51ID2 Keyboard Interface The A
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4289A-8051-09/03 Table 59. KBE Regi
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4289A-8051-09/03 AT89C51ID2 2-wire
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4289A-8051-09/03 AT89C51ID2 Descrip
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4289A-8051-09/03 AT89C51ID2 When th
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Figure 33. Format and State in the
Page 89 and 90:
Page 91 and 92:
Page 93 and 94:
Table 67. Status in Slave Receiver
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Table 68. Status in Slave Transmitt
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4289A-8051-09/03 Bit Number 1 SD1 A
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Serial Port Interface (SPI) 4289A-8
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Functional Description Figure 38 sh
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Figure 40. Data Transmission Format
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4289A-8051-09/03 Figure 43. SPI Int
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Serial Peripheral DATa register (SP
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WDT During Power Down and Idle 4289
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4289A-8051-09/03 AT89C51ID2 Power-o
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4289A-8051-09/03 Figure 44. Recomme
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Registers Table 85. EECON Register
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4289A-8051-09/03 AT89C51ID2 Flash M
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4289A-8051-09/03 Table 88. Program
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4289A-8051-09/03 Table 92. Program
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Functional Description Figure 48. B
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Boot Process Figure 49. Bootloader
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Functional Description 4289A-8051-0
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Flow Description 4289A-8051-09/03 A
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Write / Program Commands This flow
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Display Data Description Figure 55.
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Example 4289A-8051-09/03 Read funct
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4289A-8051-09/03 Table 95. ISP Comm
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Table 96. API Call Summary (Continu
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T A = -40°C to +85°C; V SS = 0V;
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External Program Memory Characteris
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External Program Memory Read Cycle
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External Data Memory Write Cycle 42
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AC Testing Input/Output Waveforms F
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Ordering Information 4289A-8051-09/
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VQFP44 4289A-8051-09/03 AT89C51ID2
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PLCC68 4289A-8051-09/03 AT89C51ID2
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4289A-8051-09/03 AT89C51ID2 Pulse W
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Atmel Corporation Atmel Operations
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Atmel AT89C51ID2 Data Sheet - Keil

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