Atmel AT89C51ID2 Data Sheet - Keil

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Reduced EMI Mode The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to reduce EMI, ALE signal can be disabled by setting AO bit. 116 AT89C51ID2 The AO bit is located in AUXR register at bit location 0. As soon as AO is set, ALE is no longer output but remains active during MOVX and MOVC instructions and external fetches. During ALE disabling, ALE pin is weakly pulled high. Table 86. AUXR Register AUXR - Auxiliary Register (8Eh) 7 6 5 4 3 2 1 0 - - M0 XRS2 XRS1 XRS0 EXTRAM AO Bit Number 7 - 6 - Bit Mnemonic Description 5 M0 Reset Value = XX00 10’HSB. XRAM’0b Not bit addressable Reserved The value read from this bit is indeterminate. Do not set this bit. Reserved The value read from this bit is indeterminate. Do not set this bit. Pulse length Cleared to stretch MOVX control: the RD/ and the WR/ pulse length is 6 clock periods (default). Set to stretch MOVX control: the RD/ and the WR/ pulse length is 30 clock periods. 4 XRS2 XRAM Size 3 XRS1 XRS2 XRS1XRS0XRAM size 0 0 0 256 bytes 0 0 1 512 bytes 0 1 0 768 bytes(default) 2 XRS0 0 1 1 1024 bytes 1 0 0 1792 bytes 1 EXTRAM 0 AO EXTRAM bit Cleared to access internal XRAM using movx @ Ri/ @ DPTR. Set to access external memory. Programmed by hardware after Power-up regarding Hardware Security Byte (HSB), default setting, XRAM selected. ALE Output bit Cleared, ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2 mode is used). (default) Set, ALE is active only during a MOVX or MOVC instruction is used. 4289A–8051–09/03
4289A–8051–09/03 AT89C51ID2 Flash Memory The Flash memory increases EPROM and ROM functionality with in-circuit electrical erasure and programming. It contains 64K bytes of program memory organized respectively in 512 pages of 128 bytes. This memory is both parallel and serial In-System Programmable (ISP). ISP allows devices to alter their own program memory in the actual end product under software control. A default serial loader (bootloader) program allows ISP of the Flash. The programming does not require external dedicated programming voltage. The necessary high programming voltage is generated on-chip using the standard V CC pins of the microcontroller. Features Flash internal program memory. Boot vector allows user provided Flash loader code to reside anywhere in the Flash memory space. This configuration provides flexibility to the user. Default loader in Boot ROM allows programming via the serial port without the need of a user provided loader. Up to 64K byte external program memory if the internal program memory is disabled (EA = 0). Programming and erase voltage with standard power supply. Read/Programming/Erase: Byte-wise read without wait state Byte or page erase and programming (10 ms) Typical programming time (64K bytes) is 22s with on chip serial bootloader Parallel programming with 87C51 compatible hardware interface to programmer Programmable security for the code in the Flash 100k write cycles 10 years data retention Flash Programming and Erasure The 64K bytes Flash is programmed by bytes or by pages of 128 bytes. It is not necessary to erase a byte or a page before programming. The programming of a byte or a page includes a self erase before programming. There are three methods of programming the Flash memory: First, the on-chip ISP bootloader may be invoked which will use low level routines to program the pages. The interface used for serial downloading of Flash is the UART. Second, the Flash may be programmed or erased in the end-user application by calling low-level routines through a common entry point in the Boot ROM. Third, the Flash may be programmed using the parallel method by using a conventional EPROM programmer. The parallel programming method used by these devices is similar to that used by EPROM 87C51 but it is not identical and the commercially available programmers need to have support for the AT89C51ID2. The bootloader and the Application Programming Interface (API) routines are located in the BOOT ROM. 117
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Features 80C52 Compatible - 8051 In
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Block Diagram Figure 1. Block Diagr
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Table 2. C51 Core SFRs 4289A-8051-0
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Table 8. PCA SFRs 4289A-8051-09/03
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Table 13. SFR Mapping F8h F0h E8h E
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11 AT89C51ID2 4289A-8051-09/03 50 4
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Table 14. Pin Description (Continue
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Oscillators 4289A-8051-09/03 AT89C5
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4289A-8051-09/03 Table 18. PCON Reg
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4289A-8051-09/03 AT89C51ID2 It is a
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4289A-8051-09/03 - FCLK CPU and FCL
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Figure 5. Mode Switching Waveforms
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4289A-8051-09/03 Table 21. CKCON1 R
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4289A-8051-09/03 Table 22. AUXR1 re
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Expanded RAM (XRAM) Figure 7. Inter
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Registers Table 23. AUXR Register A
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Reset Output 4289A-8051-09/03 AT89C
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Figure 12. Power Fail Detect Vcc 42
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Programmable Clock- Output 4289A-80
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Registers Table 24. T2CON Register
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Programmable Counter Array PCA 4289
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4289A-8051-09/03 Table 26. CMOD Reg
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Figure 16. PCA Interrupt System 428
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4289A-8051-09/03 Table 29. PCA Modu
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4289A-8051-09/03 AT89C51ID2 PCA Cap
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Figure 19. PCA High Speed Output Mo
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4289A-8051-09/03 AT89C51ID2 Serial
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4289A-8051-09/03 AT89C51ID2 The SAD
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Internal Baud Rate Generator (BRG)
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UART Registers Table 40. SADEN Regi
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4289A-8051-09/03 Table 44. T2CON Re
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4289A-8051-09/03 Table 46. BDRCON R
Page 65 and 66: 4289A-8051-09/03 AT89C51ID2 Registe
Page 67 and 68: 4289A-8051-09/03 Table 49. IPL0 Reg
Page 69 and 70: 4289A-8051-09/03 Table 51. IEN1 Reg
Page 71 and 72: 4289A-8051-09/03 Table 54. IPH1 Reg
Page 73 and 74: Power Management 4289A-8051-09/03 A
Page 75 and 76: 4289A-8051-09/03 AT89C51ID2 pins, t
Page 77 and 78: AT89C51ID2 Keyboard Interface The A
Page 79 and 80: 4289A-8051-09/03 Table 59. KBE Regi
Page 81 and 82: 4289A-8051-09/03 AT89C51ID2 2-wire
Page 83 and 84: 4289A-8051-09/03 AT89C51ID2 Descrip
Page 85 and 86: 4289A-8051-09/03 AT89C51ID2 When th
Page 87 and 88: Figure 33. Format and State in the
Page 93 and 94: Table 67. Status in Slave Receiver
Page 95 and 96: Table 68. Status in Slave Transmitt
Page 97 and 98: 4289A-8051-09/03 Bit Number 1 SD1 A
Page 99 and 100: Serial Port Interface (SPI) 4289A-8
Page 101 and 102: Functional Description Figure 38 sh
Page 103 and 104: Figure 40. Data Transmission Format
Page 105 and 106: 4289A-8051-09/03 Figure 43. SPI Int
Page 107 and 108: Serial Peripheral DATa register (SP
Page 109 and 110: WDT During Power Down and Idle 4289
Page 111 and 112: 4289A-8051-09/03 AT89C51ID2 Power-o
Page 113 and 114: 4289A-8051-09/03 Figure 44. Recomme
Page 115: Registers Table 85. EECON Register
Page 119 and 120: 4289A-8051-09/03 Table 88. Program
Page 121 and 122: 4289A-8051-09/03 Table 92. Program
Page 123 and 124: Functional Description Figure 48. B
Page 125 and 126: Boot Process Figure 49. Bootloader
Page 127 and 128: Functional Description 4289A-8051-0
Page 129 and 130: Flow Description 4289A-8051-09/03 A
Page 131 and 132: Write / Program Commands This flow
Page 133 and 134: Display Data Description Figure 55.
Page 135 and 136: Example 4289A-8051-09/03 Read funct
Page 137 and 138: 4289A-8051-09/03 Table 95. ISP Comm
Page 139 and 140: Table 96. API Call Summary (Continu
Page 141 and 142: T A = -40°C to +85°C; V SS = 0V;
Page 143 and 144: External Program Memory Characteris
Page 145 and 146: External Program Memory Read Cycle
Page 147 and 148: External Data Memory Write Cycle 42
Page 149 and 150: AC Testing Input/Output Waveforms F
Page 151 and 152: Ordering Information 4289A-8051-09/
Page 153 and 154: VQFP44 4289A-8051-09/03 AT89C51ID2
Page 155 and 156: PLCC68 4289A-8051-09/03 AT89C51ID2
Page 157 and 158: 4289A-8051-09/03 AT89C51ID2 Pulse W
Page 159: Atmel Corporation Atmel Operations
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Atmel AT89C51ID2 Data Sheet - Keil

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