Atmel AT89C51ID2 Data Sheet - Keil

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120 AT89C51ID2 Table 89. Default Values Mnemonic Definition Default value Description SBV Software Boot Vector FCh HSB Copy of the Hardware security byte 101x 1011b BSB Boot Status Byte 0FFh SSB Software Security Byte FFh Copy of the Manufacturer Code 58h ATMEL Copy of the Device ID #1: Family Code D7h C51 X2, Electrically Erasable Copy of the Device ID #2: memories size and type Copy of the Device ID #3: name and revision After programming the part by ISP, the BSB must be cleared (00h) in order to allow the application to boot at 0000h. The content of the Software Security Byte (SSB) is described in Table 89 and Table 92. To assure code protection from a parallel access, the HSB must also be at the required level. Table 90. Software Security Byte Table 91. ECh AT89C51ID2 64KB The two lock bits provide different levels of protection for the on-chip code and data, when programmed as shown to Table 92. EFh AT89C51ID2 64KB, Revision 0 7 6 5 4 3 2 1 0 - - - - - - LB1 LB0 Bit Number 7 - 6 - 5 - 4 - 3 - 2 - Bit Mnemonic Description 1-0 LB1-0 Reserved Do not clear this bit. Reserved Do not clear this bit. Reserved Do not clear this bit. Reserved Do not clear this bit. Reserved Do not clear this bit. Reserved Do not clear this bit. User Memory Lock Bits See Table 92 4289A–8051–09/03
4289A–8051–09/03 Table 92. Program Lock bits of the SSB AT89C51ID2 Note: U: unprogrammed or "one" level. P: programmed or "zero" level. X: do not care WARNING: Security level 2 and 3 should only be programmed after Flash and code verification. Flash Memory Status AT89C51ID2 parts are delivered in standard with the ISP rom bootloader. Figure 46. Flash memory possible contents FFFFh 0000h Virgin Memory Organization Default After ISP Program Lock Bits Security level LB0 LB1 1 U U No program lock features enabled. Protection description 2 P U ISP programming of the Flash is disabled. 3 X P Same as 2, also verify through ISP programming interface is disabled. After ISP or parallel programming, the possible contents of the Flash memory are summarized on the figure below: Application Virgin or application Dedicated ISP After ISP Application After parallel programming Virgin or application Dedicated ISP After parallel programming Virgin or application After parallel programming When the EA pin high, the processor fetches instructions from internal program Flash. . If the EA pin is tied low, all program memory fetches are from external memory. 121
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Features 80C52 Compatible - 8051 In
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Block Diagram Figure 1. Block Diagr
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Table 2. C51 Core SFRs 4289A-8051-0
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Table 8. PCA SFRs 4289A-8051-09/03
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Table 13. SFR Mapping F8h F0h E8h E
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11 AT89C51ID2 4289A-8051-09/03 50 4
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Table 14. Pin Description (Continue
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Oscillators 4289A-8051-09/03 AT89C5
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4289A-8051-09/03 Table 18. PCON Reg
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4289A-8051-09/03 AT89C51ID2 It is a
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4289A-8051-09/03 - FCLK CPU and FCL
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Figure 5. Mode Switching Waveforms
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4289A-8051-09/03 Table 21. CKCON1 R
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4289A-8051-09/03 Table 22. AUXR1 re
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Expanded RAM (XRAM) Figure 7. Inter
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Registers Table 23. AUXR Register A
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Reset Output 4289A-8051-09/03 AT89C
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Figure 12. Power Fail Detect Vcc 42
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Programmable Clock- Output 4289A-80
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Registers Table 24. T2CON Register
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Programmable Counter Array PCA 4289
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4289A-8051-09/03 Table 26. CMOD Reg
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Figure 16. PCA Interrupt System 428
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4289A-8051-09/03 Table 29. PCA Modu
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4289A-8051-09/03 AT89C51ID2 PCA Cap
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Figure 19. PCA High Speed Output Mo
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4289A-8051-09/03 AT89C51ID2 Serial
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4289A-8051-09/03 AT89C51ID2 The SAD
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Internal Baud Rate Generator (BRG)
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UART Registers Table 40. SADEN Regi
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4289A-8051-09/03 Table 44. T2CON Re
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4289A-8051-09/03 Table 46. BDRCON R
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4289A-8051-09/03 AT89C51ID2 Registe
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4289A-8051-09/03 Table 49. IPL0 Reg
Page 69 and 70: 4289A-8051-09/03 Table 51. IEN1 Reg
Page 71 and 72: 4289A-8051-09/03 Table 54. IPH1 Reg
Page 73 and 74: Power Management 4289A-8051-09/03 A
Page 75 and 76: 4289A-8051-09/03 AT89C51ID2 pins, t
Page 77 and 78: AT89C51ID2 Keyboard Interface The A
Page 79 and 80: 4289A-8051-09/03 Table 59. KBE Regi
Page 81 and 82: 4289A-8051-09/03 AT89C51ID2 2-wire
Page 83 and 84: 4289A-8051-09/03 AT89C51ID2 Descrip
Page 85 and 86: 4289A-8051-09/03 AT89C51ID2 When th
Page 87 and 88: Figure 33. Format and State in the
Page 93 and 94: Table 67. Status in Slave Receiver
Page 95 and 96: Table 68. Status in Slave Transmitt
Page 97 and 98: 4289A-8051-09/03 Bit Number 1 SD1 A
Page 99 and 100: Serial Port Interface (SPI) 4289A-8
Page 101 and 102: Functional Description Figure 38 sh
Page 103 and 104: Figure 40. Data Transmission Format
Page 105 and 106: 4289A-8051-09/03 Figure 43. SPI Int
Page 107 and 108: Serial Peripheral DATa register (SP
Page 109 and 110: WDT During Power Down and Idle 4289
Page 111 and 112: 4289A-8051-09/03 AT89C51ID2 Power-o
Page 113 and 114: 4289A-8051-09/03 Figure 44. Recomme
Page 115 and 116: Registers Table 85. EECON Register
Page 117 and 118: 4289A-8051-09/03 AT89C51ID2 Flash M
Page 119: 4289A-8051-09/03 Table 88. Program
Page 123 and 124: Functional Description Figure 48. B
Page 125 and 126: Boot Process Figure 49. Bootloader
Page 127 and 128: Functional Description 4289A-8051-0
Page 129 and 130: Flow Description 4289A-8051-09/03 A
Page 131 and 132: Write / Program Commands This flow
Page 133 and 134: Display Data Description Figure 55.
Page 135 and 136: Example 4289A-8051-09/03 Read funct
Page 137 and 138: 4289A-8051-09/03 Table 95. ISP Comm
Page 139 and 140: Table 96. API Call Summary (Continu
Page 141 and 142: T A = -40°C to +85°C; V SS = 0V;
Page 143 and 144: External Program Memory Characteris
Page 145 and 146: External Program Memory Read Cycle
Page 147 and 148: External Data Memory Write Cycle 42
Page 149 and 150: AC Testing Input/Output Waveforms F
Page 151 and 152: Ordering Information 4289A-8051-09/
Page 153 and 154: VQFP44 4289A-8051-09/03 AT89C51ID2
Page 155 and 156: PLCC68 4289A-8051-09/03 AT89C51ID2
Page 157 and 158: 4289A-8051-09/03 AT89C51ID2 Pulse W
Page 159: Atmel Corporation Atmel Operations
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Atmel AT89C51ID2 Data Sheet - Keil

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