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Atmel AT89C51ID2 Data Sheet - Keil

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Table 66. Status in Master Receiver Mode<br />

Status<br />

Code<br />

SSSTA<br />

08h<br />

10h<br />

38h<br />

40h<br />

48h<br />

50h<br />

58h<br />

Status of the Twowire<br />

Bus and Twowire<br />

Hardware<br />

A START condition has<br />

been transmitted<br />

A repeated START<br />

condition has been<br />

transmitted<br />

Arbitration lost in<br />

SLA+R or NOT ACK<br />

bit<br />

SLA+R has been<br />

transmitted; ACK has<br />

been received<br />

SLA+R has been<br />

transmitted; NOT ACK<br />

has been received<br />

<strong>Data</strong> byte has been<br />

received; ACK has<br />

been returned<br />

<strong>Data</strong> byte has been<br />

received; NOT ACK<br />

has been returned<br />

90 <strong>AT89C51ID2</strong><br />

To/From SSDAT<br />

Application software response<br />

To SSCON<br />

SSSTA SSSTO SSI SSAA<br />

Next Action Taken by Two-wire Hardware<br />

Write SLA+R X 0 0 X SLA+R will be transmitted.<br />

Write SLA+R<br />

Write SLA+W<br />

No SSDAT action<br />

No SSDAT action<br />

No SSDAT action<br />

No SSDAT action<br />

No SSDAT action<br />

No SSDAT action<br />

No SSDAT action<br />

Read data byte<br />

Read data byte<br />

Read data byte<br />

Read data byte<br />

Read data byte<br />

X<br />

X<br />

0<br />

1<br />

0<br />

0<br />

1<br />

0<br />

1<br />

0<br />

0<br />

1<br />

0<br />

1<br />

0<br />

0<br />

0<br />

0<br />

0<br />

0<br />

0<br />

1<br />

1<br />

0<br />

0<br />

0<br />

1<br />

1<br />

0<br />

0<br />

0<br />

0<br />

0<br />

0<br />

0<br />

0<br />

0<br />

0<br />

0<br />

0<br />

0<br />

0<br />

X<br />

X<br />

X<br />

X<br />

0<br />

1<br />

X<br />

X<br />

X<br />

0<br />

1<br />

X<br />

X<br />

X<br />

SLA+R will be transmitted.<br />

SLA+W will be transmitted.<br />

Logic will switch to master transmitter mode.<br />

Two-wire bus will be released and not addressed<br />

slave mode will be entered.<br />

A START condition will be transmitted when the bus<br />

becomes free.<br />

<strong>Data</strong> byte will be received and NOT ACK will be<br />

returned.<br />

<strong>Data</strong> byte will be received and ACK will be returned.<br />

Repeated START will be transmitted.<br />

STOP condition will be transmitted and SSSTO flag<br />

will be reset.<br />

STOP condition followed by a START condition will<br />

be transmitted and SSSTO flag will be reset.<br />

<strong>Data</strong> byte will be received and NOT ACK will be<br />

returned.<br />

<strong>Data</strong> byte will be received and ACK will be returned.<br />

Repeated START will be transmitted.<br />

STOP condition will be transmitted and SSSTO flag<br />

will be reset.<br />

STOP condition followed by a START condition will<br />

be transmitted and SSSTO flag will be reset.<br />

4289A–8051–09/03

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