Atmel AT89C51ID2 Data Sheet - Keil

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Design Considerations Oscillators Control PwdOscA and PwdOscB signals are generated in the Clock generator and used to control the hard blocks of oscillators A and B. PwdOscA =’1’ stops OscA PwdOscB =’1’ stops OscB The following tables summarize the Operating modes: Prescaler Divider A hardware RESET puts the prescaler divider in the following state: – CKRL = FFh: FCLK CPU = FCLK PERIPH = FOSCA /2 (Standard C51 feature) CKS signal selects OSCA or OSCB: F CLK OUT = FOSCA or FOSCB Any value between FFh down to 00h can be written by software into CKRL register in order to divide frequency of the selected oscillator: – CKRL = 00h: minimum frequency FCLK CPU = FCLK PERIPH = FOSCA /1020 (Standard Mode) FCLK CPU = FCLK PERIPH = FOSCA /510 (X2 Mode) – CKRL = FFh: maximum frequency FCLK CPU = FCLK PERIPH = FOSCA /2 (Standard Mode) FCLK CPU = FCLK PERIPH = FOSCA (X2 Mode) 20 <strong>AT89C51ID2</strong> Table 19. Overview (Continued) PCON.1 PCON.0 OscBEn OscAEn CKS Selected Mode Comment 0 1 X 1 1 IDLE MODE A 0 1 1 X 0 IDLE MODE B 1 X X 1 X POWER DOWN MODE The CPU is off, OscA supplies the peripherals, OscB can be disabled (OscBEn = 0) The CPU is off, OscB supplies the peripherals, OscA can be disabled (OscAEn = 0) The CPU and peripherals are off, OscA and OscB are stopped PCON.1 OscAEn PwdOscA Comments 0 1 0 OscA running 1 X 1 0 0 1 OscA stopped by Power-down mode OscA stopped by clearing OscAEn PCON.1 OscBEn PwdOscB Comments 0 1 0 OscB running 1 X 1 0 0 1 OscB stopped by Power-down mode OscB stopped by clearing OscBEn 4289A–8051–09/03
4289A–8051–09/03 – FCLK CPU and FCLK PERIPH , for CKRL0xFF In X2 Mode: In X1 Mode: F CPU F CPU Timer 0: Clock Inputs Figure 3. Timer 0: Clock Inputs FCLK PERIPH :6 T0 pin Sub Clock Gate INT0 TR0 0 1 SCLKT0 OSCCON = FCLKPERIPH = FCLKPERIPH 0 1 C/T TMOD F OSCA = ---------------------------------------------- 2 × ( 255 – CKRL) F OSCA = ---------------------------------------------- 4 × ( 255 – CKRL) Control Timer 0 <strong>AT89C51ID2</strong> Note: The SCLKT0 bit in OSCCON register allows to select Timer 0 Subsidiary clock. SCLKT0 = 0: Timer 0 uses the standard T0 pin as clock input (Standard mode) SCLKT0 = 1: Timer 0 uses the special Sub Clock as clock input, this feature can be use as periodic interrupt for time clock. 21
Page 1 and 2: Features 80C52 Compatible - 8051 In
Page 3 and 4: Block Diagram Figure 1. Block Diagr
Page 5 and 6: Table 2. C51 Core SFRs 4289A-8051-0
Page 7 and 8: Table 8. PCA SFRs 4289A-8051-09/03
Page 9 and 10: Table 13. SFR Mapping F8h F0h E8h E
Page 11 and 12: 11 AT89C51ID2 4289A-8051-09/03 50 4
Page 13 and 14: Table 14. Pin Description (Continue
Page 15 and 16: Oscillators 4289A-8051-09/03 AT89C5
Page 17 and 18: 4289A-8051-09/03 Table 18. PCON Reg
Page 19: 4289A-8051-09/03 AT89C51ID2 It is a
Page 23 and 24: Figure 5. Mode Switching Waveforms
Page 25 and 26: 4289A-8051-09/03 Table 21. CKCON1 R
Page 27 and 28: 4289A-8051-09/03 Table 22. AUXR1 re
Page 29 and 30: Expanded RAM (XRAM) Figure 7. Inter
Page 31 and 32: Registers Table 23. AUXR Register A
Page 33 and 34: Reset Output 4289A-8051-09/03 AT89C
Page 35 and 36: Figure 12. Power Fail Detect Vcc 42
Page 37 and 38: Programmable Clock- Output 4289A-80
Page 39 and 40: Registers Table 24. T2CON Register
Page 41 and 42: Programmable Counter Array PCA 4289
Page 43 and 44: 4289A-8051-09/03 Table 26. CMOD Reg
Page 45 and 46: Figure 16. PCA Interrupt System 428
Page 47 and 48: 4289A-8051-09/03 Table 29. PCA Modu
Page 49 and 50: 4289A-8051-09/03 AT89C51ID2 PCA Cap
Page 51 and 52: Figure 19. PCA High Speed Output Mo
Page 53 and 54: 4289A-8051-09/03 AT89C51ID2 Serial
Page 55 and 56: 4289A-8051-09/03 AT89C51ID2 The SAD
Page 57 and 58: Internal Baud Rate Generator (BRG)
Page 59 and 60: UART Registers Table 40. SADEN Regi
Page 61 and 62: 4289A-8051-09/03 Table 44. T2CON Re
Page 63 and 64: 4289A-8051-09/03 Table 46. BDRCON R
Page 65 and 66: 4289A-8051-09/03 AT89C51ID2 Registe
Page 67 and 68: 4289A-8051-09/03 Table 49. IPL0 Reg
Page 69 and 70: 4289A-8051-09/03 Table 51. IEN1 Reg
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4289A-8051-09/03 Table 54. IPH1 Reg
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Power Management 4289A-8051-09/03 A
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4289A-8051-09/03 AT89C51ID2 pins, t
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AT89C51ID2 Keyboard Interface The A
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4289A-8051-09/03 Table 59. KBE Regi
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4289A-8051-09/03 AT89C51ID2 2-wire
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4289A-8051-09/03 AT89C51ID2 Descrip
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4289A-8051-09/03 AT89C51ID2 When th
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Figure 33. Format and State in the
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Page 91 and 92:
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Table 67. Status in Slave Receiver
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Table 68. Status in Slave Transmitt
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4289A-8051-09/03 Bit Number 1 SD1 A
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Serial Port Interface (SPI) 4289A-8
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Functional Description Figure 38 sh
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Figure 40. Data Transmission Format
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4289A-8051-09/03 Figure 43. SPI Int
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Serial Peripheral DATa register (SP
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WDT During Power Down and Idle 4289
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4289A-8051-09/03 AT89C51ID2 Power-o
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4289A-8051-09/03 Figure 44. Recomme
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Registers Table 85. EECON Register
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4289A-8051-09/03 AT89C51ID2 Flash M
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4289A-8051-09/03 Table 88. Program
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4289A-8051-09/03 Table 92. Program
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Functional Description Figure 48. B
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Boot Process Figure 49. Bootloader
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Functional Description 4289A-8051-0
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Flow Description 4289A-8051-09/03 A
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Write / Program Commands This flow
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Display Data Description Figure 55.
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Example 4289A-8051-09/03 Read funct
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4289A-8051-09/03 Table 95. ISP Comm
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Table 96. API Call Summary (Continu
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T A = -40°C to +85°C; V SS = 0V;
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External Program Memory Characteris
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External Program Memory Read Cycle
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External Data Memory Write Cycle 42
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AC Testing Input/Output Waveforms F
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Ordering Information 4289A-8051-09/
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VQFP44 4289A-8051-09/03 AT89C51ID2
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PLCC68 4289A-8051-09/03 AT89C51ID2
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4289A-8051-09/03 AT89C51ID2 Pulse W
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Atmel Corporation Atmel Operations
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Atmel AT89C51ID2 Data Sheet - Keil

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