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4289A–8051–09/03<br />
Table 54. IPH1 Register<br />
IPH1 - Interrupt Priority High Register (B3h)<br />
Reset Value = XXXX X000b<br />
Not bit addressable<br />
<strong>AT89C51ID2</strong><br />
7 6 5 4 3 2 1 0<br />
- - - - - SPIH TWIH KBDH<br />
Bit<br />
Number<br />
7 -<br />
6 -<br />
5 -<br />
4 -<br />
3 -<br />
Bit<br />
Mnemonic Description<br />
2 SPIH<br />
1 TWIH<br />
0 KBDH<br />
Reserved<br />
The value read from this bit is indeterminate. Do not set this bit.<br />
Reserved<br />
The value read from this bit is indeterminate. Do not set this bit.<br />
Reserved<br />
The value read from this bit is indeterminate. Do not set this bit.<br />
Reserved<br />
The value read from this bit is indeterminate. Do not set this bit.<br />
Reserved<br />
The value read from this bit is indeterminate. Do not set this bit.<br />
SPI interrupt Priority High bit<br />
SPIH SPILPriority Level<br />
0 0 Lowest<br />
0 1<br />
1 0<br />
1 1 Highest<br />
TWI interrupt Priority High bit<br />
TWIH TWILPriority Level<br />
0 0 Lowest<br />
0 1<br />
1 0<br />
1 1 Highest<br />
Keyboard interrupt Priority High bit<br />
KB DH KBDLPriority Level<br />
0 0 Lowest<br />
0 1<br />
1 0<br />
1 1 Highest<br />
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