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Figure 34. Format and State in the Master Receiver Mode<br />
MR<br />
4289A–8051–09/03<br />
Successfull<br />
transmission<br />
to a slave<br />
receiver<br />
Next transfer<br />
started with a<br />
repeated start<br />
condition<br />
Not acknowledge<br />
received after the<br />
slave address<br />
Arbitration lost in slave<br />
address or acknowledge bit<br />
Arbitration lost and<br />
addressed as slave<br />
S SLA R A <strong>Data</strong><br />
08h 40h 50h<br />
58h<br />
From master to slave<br />
From slave to master<br />
A P<br />
48h<br />
A or A continues<br />
38h<br />
Other master<br />
A continues<br />
68h<br />
Other master<br />
78h B0h<br />
<strong>Data</strong> A<br />
n<br />
A <strong>Data</strong> A P<br />
38h<br />
<strong>AT89C51ID2</strong><br />
S SLA R<br />
10h<br />
Other master<br />
A continues<br />
To corresponding<br />
states in slave mode<br />
W<br />
MT<br />
Any number of data bytes and their associated<br />
acknowledge bits<br />
This number (contained in SSCS) corresponds<br />
to a defined state of the 2-wire bus<br />
89
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