Atmel AT89C51ID2 Data Sheet - Keil

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Functional Block Diagram Figure 2. Functional Oscillator Block Diagram XtalA1 XtalA2 PwdOscA Operating Modes Reset A hardware RESET puts the Clock generator in the following state: Functional Modes OscA OscAEn OSCCON XtalB1 XtalB2 FOSCA PwdOscB 18 <strong>AT89C51ID2</strong> Reset :2 OscB OscBEn OSCCON CKRL 1 0 X2 CKCON0 The selected oscillator depends on OSC bit in Hardware Security Byte (HSB). HSB.OSC = 1 (Oscillator A selected) OscAEn = 1 & OscBEn = 0: OscA is running, OscB is stopped. CKS = 1: OscA is selected for CPU. HSB.OSC = 0 (Oscillator B selected) OscAEn = 0 & OscBEn = 1: OscB is running, OscA is stopped. CKS = 0: OscB is selected for CPU. CLK Peripheral Clock PERIPH Normal Modes CPU and Peripherals clock depend on the software selection using CKCON0, CKCON1 and CKRL registers CKS bit in CKSEL register selects either OscA or OscB CKRL register determines the frequency of the OscA clock. Reload 8-bit Prescaler-Divider 0 1 CKRL=0xFF? FOSCB 1 0 CKS CKSEL Idle CLK CPU :128 Sub Clock CPU clock 4289A–8051–09/03
4289A–8051–09/03 <strong>AT89C51ID2</strong> It is always possible to switch dynamically by software from OscA to OscB, and vice versa by changing CKS bit. Idle Modes IDLE modes are achieved by using any instruction that writes into PCON.0 bit (IDL) IDLE modes A and B depend on previous software sequence, prior to writing into PCON.0 bit: IDLE MODE A: OscA is running (OscAEn = 1) and selected (CKS = 1) IDLE MODE B: OscB is running (OscBEn = 1) and selected (CKS = 0) The unused oscillator OscA or OscB can be stopped by software by clearing OscAEn or OscBEn respectively. IDLE mode can be canceled either by Reset, or by activation of any enabled interruption In both cases, PCON.0 bit (IDL) is cleared by hardware Exit from IDLE modes will leave Oscillators control bits (OscEnA, OscEnB, CKS) unchanged. Power Down Modes POWER DOWN modes are achieved by using any instruction that writes into PCON.1 bit (PD) POWER DOWN modes A and B depend on previous software sequence, prior to writing into PCON.1 bit: Both OscA and OscB will be stopped. POWER DOWN mode can be cancelled either by a hardware Reset, an external interruption, or the keyboard interrupt. By Reset signal: The CPU will restart according to OSC bit in Hardware Security Bit (HSB) register. By INT0 or INT1 interruption, if enabled: (standard behavioral), request on Pads must be driven low enough to ensure correct restart of the oscillator which was selected when entering in Power down. By keyboard Interrupt if enabled: a hardware clear of the PCON.1 flag ensure the restart of the oscillator which was selected when entering in Power down. Table 19. Overview PCON.1 PCON.0 OscBEn OscAEn CKS Selected Mode Comment 0 0 0 1 1 0 0 1 1 1 0 0 1 0 0 0 0 1 1 0 NORMAL MODE A, OscB stopped NORMAL MODE A, OscB running NORMAL MODE B, OscA stopped NORMAL MODE B, OscA running X X 0 0 X INVALID X X X 0 1 INVALID X X 0 X 0 INVALID Default mode after power-up or Warm Reset Default mode after power-up or Warm Reset + OscB running OscB running and selected OscB running and selected + OscA running OscA & OscB cannot be stopped at the same time OscA must not be stopped, as used for CPU and peripherals OscB must not be stopped as used for CPU and peripherals 19
Page 1 and 2: Features 80C52 Compatible - 8051 In
Page 3 and 4: Block Diagram Figure 1. Block Diagr
Page 5 and 6: Table 2. C51 Core SFRs 4289A-8051-0
Page 7 and 8: Table 8. PCA SFRs 4289A-8051-09/03
Page 9 and 10: Table 13. SFR Mapping F8h F0h E8h E
Page 11 and 12: 11 AT89C51ID2 4289A-8051-09/03 50 4
Page 13 and 14: Table 14. Pin Description (Continue
Page 15 and 16: Oscillators 4289A-8051-09/03 AT89C5
Page 17: 4289A-8051-09/03 Table 18. PCON Reg
Page 21 and 22: 4289A-8051-09/03 - FCLK CPU and FCL
Page 23 and 24: Figure 5. Mode Switching Waveforms
Page 25 and 26: 4289A-8051-09/03 Table 21. CKCON1 R
Page 27 and 28: 4289A-8051-09/03 Table 22. AUXR1 re
Page 29 and 30: Expanded RAM (XRAM) Figure 7. Inter
Page 31 and 32: Registers Table 23. AUXR Register A
Page 33 and 34: Reset Output 4289A-8051-09/03 AT89C
Page 35 and 36: Figure 12. Power Fail Detect Vcc 42
Page 37 and 38: Programmable Clock- Output 4289A-80
Page 39 and 40: Registers Table 24. T2CON Register
Page 41 and 42: Programmable Counter Array PCA 4289
Page 43 and 44: 4289A-8051-09/03 Table 26. CMOD Reg
Page 45 and 46: Figure 16. PCA Interrupt System 428
Page 47 and 48: 4289A-8051-09/03 Table 29. PCA Modu
Page 49 and 50: 4289A-8051-09/03 AT89C51ID2 PCA Cap
Page 51 and 52: Figure 19. PCA High Speed Output Mo
Page 53 and 54: 4289A-8051-09/03 AT89C51ID2 Serial
Page 55 and 56: 4289A-8051-09/03 AT89C51ID2 The SAD
Page 57 and 58: Internal Baud Rate Generator (BRG)
Page 59 and 60: UART Registers Table 40. SADEN Regi
Page 61 and 62: 4289A-8051-09/03 Table 44. T2CON Re
Page 63 and 64: 4289A-8051-09/03 Table 46. BDRCON R
Page 65 and 66: 4289A-8051-09/03 AT89C51ID2 Registe
Page 67 and 68: 4289A-8051-09/03 Table 49. IPL0 Reg
Page 69 and 70:
4289A-8051-09/03 Table 51. IEN1 Reg
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4289A-8051-09/03 Table 54. IPH1 Reg
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Power Management 4289A-8051-09/03 A
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4289A-8051-09/03 AT89C51ID2 pins, t
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AT89C51ID2 Keyboard Interface The A
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4289A-8051-09/03 Table 59. KBE Regi
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4289A-8051-09/03 AT89C51ID2 2-wire
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4289A-8051-09/03 AT89C51ID2 Descrip
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4289A-8051-09/03 AT89C51ID2 When th
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Figure 33. Format and State in the
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Page 91 and 92:
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Table 67. Status in Slave Receiver
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Table 68. Status in Slave Transmitt
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4289A-8051-09/03 Bit Number 1 SD1 A
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Serial Port Interface (SPI) 4289A-8
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Functional Description Figure 38 sh
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Figure 40. Data Transmission Format
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4289A-8051-09/03 Figure 43. SPI Int
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Serial Peripheral DATa register (SP
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WDT During Power Down and Idle 4289
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4289A-8051-09/03 AT89C51ID2 Power-o
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4289A-8051-09/03 Figure 44. Recomme
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Registers Table 85. EECON Register
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4289A-8051-09/03 AT89C51ID2 Flash M
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4289A-8051-09/03 Table 88. Program
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4289A-8051-09/03 Table 92. Program
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Functional Description Figure 48. B
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Boot Process Figure 49. Bootloader
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Functional Description 4289A-8051-0
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Flow Description 4289A-8051-09/03 A
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Write / Program Commands This flow
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Display Data Description Figure 55.
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Example 4289A-8051-09/03 Read funct
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4289A-8051-09/03 Table 95. ISP Comm
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Table 96. API Call Summary (Continu
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T A = -40°C to +85°C; V SS = 0V;
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External Program Memory Characteris
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External Program Memory Read Cycle
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External Data Memory Write Cycle 42
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AC Testing Input/Output Waveforms F
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Ordering Information 4289A-8051-09/
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VQFP44 4289A-8051-09/03 AT89C51ID2
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PLCC68 4289A-8051-09/03 AT89C51ID2
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4289A-8051-09/03 AT89C51ID2 Pulse W
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Atmel Corporation Atmel Operations
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Atmel AT89C51ID2 Data Sheet - Keil

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