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70 <strong>AT89C51ID2</strong><br />
Table 52. IPL1 Register<br />
IPL1 - Interrupt Priority Register (B2h)<br />
Table 53.<br />
7 6 5 4 3 2 1 0<br />
- - - - - SPIL TWIL KBDL<br />
Bit<br />
Number<br />
7 -<br />
6 -<br />
5 -<br />
4 -<br />
3 -<br />
Bit<br />
Mnemonic Description<br />
2 SPIL<br />
1 TWIL<br />
0 KBDL<br />
Reset Value = XXXX X000b<br />
Bit addressable<br />
Reserved<br />
The value read from this bit is indeterminate. Do not set this bit.<br />
Reserved<br />
The value read from this bit is indeterminate. Do not set this bit.<br />
Reserved<br />
The value read from this bit is indeterminate. Do not set this bit.<br />
Reserved<br />
The value read from this bit is indeterminate. Do not set this bit.<br />
Reserved<br />
The value read from this bit is indeterminate. Do not set this bit.<br />
SPI interrupt Priority bit<br />
Refer to SPIH for priority level.<br />
TWI interrupt Priority bit<br />
Refer to TWIH for priority level.<br />
Keyboard interrupt Priority bit<br />
Refer to KBDH for priority level.<br />
4289A–8051–09/03