SERWIS ELEKTRONIKI

Chassis LC03E firmy Philips
HSYNC1_PORT1
VSYNC1_PORT1
FIELD ID1_PORT1
IN_CLK1_PORT1
HSYNC2_PORT1
VSYNC2_PORT1
FIELD ID2_PORT1
VDD1
VSS
IN_CLK2_PORT1
B/Cb/D1_0
B/Cb/D1_1
B/Cb/D1_2
B/Cb/D1_3
B/Cb/D1_4
VDDcore1
VSScore
B/Cb/D1_5
B/Cb/D1_6
B/Cb/D1_7
R/Cr/Cb Cr_0
R/Cr/Cb Cr_1
R/Cr/Cb Cr_2
R/Cr/Cb Cr_3
R/Cr/Cb Cr_4
R/Cr/Cb Cr_5
R/Cr/Cb Cr_6
R/Cr/Cb Cr_7
G/Y/Y_0
VDD2
VSS
G/Y/Y_1
G/Y/Y_2
G/Y/Y_3
G/Y/Y_4
VDDcore2
VSScore
G/Y/Y_5
G/Y/Y_6
G/Y/Y_7
IN_SEL
TEST
DEV_ADDR1
DEV_ADDR0
SCLK
SDATA
RESET_N
VDD3
VSS
SDRAM DATA(0)
SDRAM DATA(1)
SDRAM DATA(2)
1
5
10
15
20
25
30
35
40
45
50
55
205
Port 2
8-bit
656 Input
Port 1
8/16/24-bit
RGB/YCrCb
Input
Input Processor
with Auto Sync
and auto Adjust
Clock
Generation
PLLs
Noise Reducer,
Deinterlacer, Frame
Rate Converter and
SDRAM interface
2Mx32
SDRAM
(external)
7. Tworzenie grafiki OSD dla sygna³ów: H D i z komputera PC
Z uk³adem JagASM-A4 wspó³pracuj¹ 2 pamiêci SDRAM
7471, 7472 o pojemnoœci 32×2Mbajty ka¿da. Pamiêci te o symbolu
K4S643232E-TC50 s³u¿¹ do zapamiêtania danych obrazu
przetwarzanego. Przed wejœciem do uk³adu 7402 sygna³y z komputera
PC s¹ wstêpnie obrabiane przez uk³ady: 7201 74HC4052D,
7203 74LVC14 oraz uk³ady klampowania impulsów synchronizuj¹cych
na tranzystorach 7204, 7205 BC847B. Z uk³adu JagASM-A4
otrzymujemy sygna³y 3×8 bitów: P RB, P GB, P BB oraz
sygna³y synchronizacji obrazu: F HSYNC, F VSYNC, F DE, F SHCLK. Te
60
200
Vertical and
Horizontal
Scalers
42 SERWIS ELEKTRONIKI 1/2007
65
195
70
190
75
185
80
180
85
Vertical and
Horizontal
Enhancers
175
Output
Processor with
Sync Generation
and DACs
90
170
95
165
16/20/24-bit
RBG/YCrCb
Digital Outputs
RBG/YCrCb
Analog Outputs
HSYNC_PORT2
VSYNC_PORT2
FIELD ID_PORT2
D1_IN_7
D1_IN_6
D1_IN_5
D1_IN_4
D1_IN_3
D1_IN_2
D1_IN_1
VSScore
VDDcore8
D1_IN_0
IN_CLK_PORT2
VSS
VDD9
XTAL OUT
XTAL IN
TEST2
TEST1
TEST0
DAC_PVDD
DAC_GR_AVDD
DAC_GR_AVSS
DAC_AVSS
DAC_AVDD
DAC_VREFIN
DAC_VREFOUT
DAC_RSET
DAC_COMP
DAC_AVSSR
DAC_AVDDR
DAC_R_OUT
DAC_AVSSG
DAC_AVDDG
DAC_G_OUT
DAC_AVSSB
DAC_AVDDB
DAC_B_OUT
DAC_VSS
DAC_VDD
DAC_PVSS
AVSS_PLL_FE
AVDD_PLL_FE
AVDD_PLL_SDI
AVSS_PLL_SDI
AVSS_PLL_BE2
AVDD_PLL_BE2
AVDD_PLL_BE1
AVSS_PLL_BE1
PLL_PVSS
PLL_PVDD
SDRAM DATA(3)
SDRAM DATA(4)
SDRAM DATA(5)
SDRAM DATA(6)
SDRAM DATA(7)
SDRAM DATA(8)
SDRAM DATA(9)
SDRAM DATA(10)
SDRAM DATA(11)
VDD4
VSS
SDRAM DATA(12)
SDRAM DATA(13)
SDRAM DATA(14)
SDRAM DATA(15)
VDDcore3
VSScore
SDRAM DATA(16)
SDRAM DATA(17)
SDRAM DATA(18)
SDRAM DATA(19)
SDRAM DATA(20)
SDRAM DATA(21)
SDRAM DATA(22)
SDRAM DATA(23)
SDRAM DATA(24)
SDRAM DATA(25)
VDDcore4
VSScore
SDRAM DATA(26)
SDRAM DATA(27)
SDRAM DATA(28)
SDRAM DATA(29)
SDRAM DATA(30)
SDRAM DATA(31)
VDD5
VSS
TEST IN
SDRAM ADDR(10)
SDRAM ADDR(9)
SDRAM ADDR(8)
SDRAM ADDR(7)
SDRAM ADDR(6)
VDDcore5
VSScore
SDRAM ADDR(5)
SDRAM ADDR(4)
SDRAM ADDR(3)
SDRAM ADDR(2)
SDRAM ADDR(1)
SDRAM ADDR(0)
SDRAM WEN
Rys. 9. Schemat blokowy oraz wyprowadzenia uk³adu FLI2300-AB.
sygna³y steruj¹ uk³ad wyjœcia LVDS zbudowany na uk³adzie
7501 DS90C385MTDX. Na wyjœciu tego uk³adu otrzymujemy
sygna³y steruj¹ce panel LCD poprzez z³¹cze 1506.
W OTV Philips chassis LC03E zastosowano nastêpuj¹ce panele
LCD:
• 15” LC151X01-C3P1;
• 17” LM171W01-B3;
• 23” LC230W01-A2.
W/w panele maj¹ nastêpuj¹ce cechy:
Maksymalna rozdzielczoœæ (H×V):
100
160
155
150
145
140
135
130
125
120
115
110
105
OE
G/Y/Y_OUT_7
G/Y/Y_OUT_6
G/Y/Y_OUT_5
G/Y/Y_OUT_4
G/Y/Y_OUT_3
G/Y/Y_OUT_2
G/Y/Y_OUT_1
G/Y/Y_OUT_0
VSS
VDD8
R/V/Pr_OUT_7
R/V/Pr_OUT_6
R/V/Pr_OUT_5
R/V/Pr_OUT_4
R/V/Pr_OUT_3
R/V/Pr_OUT_2
VSScore
VDDcore7
R/V/Pr_OUT_1
R/V/Pr_OUT_0
B/U/Pb_OUT_7
B/U/Pb_OUT_6
B/U/Pb_OUT_5
B/U/Pb_OUT_4
B/U/Pb_OUT_3
B/U/Pb_OUT_2
VSS
VDD7
B/U/Pb_OUT_1
B/U/Pb_OUT_0
CLKOUT
VSScore
VDDcore6
CTLOUT4
CTLOUT3
CTLOUT2
CTLOUT1
CTLOUT0
TEST OUT1
TEST OUT0
TEST3
SDRAM CLKIN
VSS
VDD6
SDRAM CLKOUT
SDRAM DQM
SDRAM CSN
SDRAM BA0
SDRAM BA1
SDRAM CASN
SDRAM RASN