boylistad

a c
E
Admittance diagram: As shown in Fig. 15.68.
I R and I C
I = 10 A ∠ 0°
I 10 A �0°
E � IZT ����� �10 V ��53.13°
YT 1S�53.13°
IR � (E �v)(G �0°)
� (10 V ��53.13°)(0.6 S �0°) � 6 A ��53.13°
IC � (E �v)(BC �90°)
� (10 V ��53.13°)(0.8 S �90°) � 8 A �36.87°
Kirchhoff’s current law: At node a,
I � I R � I C � 0
or I � I R � I C
+
E
–
which can also be verified (as for the R-L network) through vector
algebra.
Phasor diagram: The phasor diagram of Fig. 15.69 indicates that
E is in phase with the current through the resistor I R and lags the capacitive
current I C by 90°.
Time domain:
e � �2�(10) sin(qt � 53.13°) � 14.14 sin(qt � 53.13°)
iR � �2�(6) sin(qt � 53.13°) � 8.48 sin(qt � 53.13°)
iC � �2�(8) sin(qt � 36.87°) � 11.31 sin(qt � 36.87°)
IR
R 1.67 �
a
I C
1.25 �
FIG. 15.67
Applying phasor notation to the network of Fig. 15.66.
B C ∠ 90° = 0.8 S ∠ 90°
j
53.13°
X C
Y T = 1 S ∠ 53.13°
G ∠ 0° = 0.6 S ∠ 0°
FIG. 15.68
Admittance diagram for the parallel R-C network of Fig. 15.66.
+
PARALLEL ac NETWORKS ⏐⏐⏐ 663
j
36.87°
53.13°
I R
FIG. 15.69
Phasor diagram for the parallel R-C network
of Fig. 15.66.
I C
E
I
+