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714 ⏐⏐⏐ SERIES-PARALLEL ac NETWORKS
I 4 mA ∠ 0°
Z 1
Z 2
I L
V L
FIG. 16.11
Network of Fig. 16.10 following the assignment
of the block impedances.
+
–
I 4 mA ∠ 0°
Transistor equivalent
network
R o
50 k� R C
Coupling
capacitor
Biasing
network
10 �F �
3.3 k�
FIG. 16.10
Basic transistor amplifier.
Next stage
R i 1 k� V L
a. Determine VL for the network of Fig. 16.10 at a frequency of
100 Hz.
b. Repeat part (a) at a frequency of 20 kHz.
c. Compare the results of parts (a) and (b).
Solutions:
a. The network is redrawn with subscripted impedances in Fig.
16.11.
Z1 � 50 k� �0° � 3.3 k� �0° � 3.096 k� �0°
Z2 � Ri � j XC 1
1
At f � 100 Hz: XC ����� �159.16 �
2pfC 2p(100 Hz)(10 mF)
and Z2 � 1 k� �j 159.16 �
Current divider rule:
Z1I (3.096 k� �0°)(4 mA �0°)
IL ������� Z1 � Z2 3.096 k��1 k��j 159.16 �
12.384 A �0° 12.384 A �0°
��� ���
4096 � j 159.16 4099 ��2.225°
� 3.021 mA �2.225°
and VL � ILZR � (3.021 mA �2.225°)(1 k� �0°)
� 3.021 V �2.225°
1
1
b. At f � 20 kHz: XC ������ � 0.796 �
2pfC 2p(20 kHz)(10 mF)
Note the dramatic change in XC with frequency. Obviously, the
higher the frequency, the better the short-circuit approximation for
XC for ac conditions.
Z2 � 1 k��j 0.796 �
Current divider rule:
Z1I (3.096 k� �0°)(4 mA �0°)
IL ������� Z1 � Z2 3.096 k��1 k��j 0.796 �
12.384 A �0° 12.384 A �0°
��� ���
4096 � j 0.796 � 4096 ��0.011°
� 3.023 mA �0.011°
+
–