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The total impedance is defined by<br />

ZT � Z1 � Z2 with<br />

Z1 � R �0° � 1 � �0°<br />

(XC ��90°)(XL �90°) (2 � ��90°)(3 � �90°)<br />

Z2 � ZC � ZL ���� � ���<br />

�j XC � j XL �j 2 ��j 3 �<br />

6 � �0° 6 � �0°<br />

�����6 � ��90°<br />

j 1 1 �90°<br />

and<br />

ZT � Z1 � Z2 � 1 ��j 6 ��6.08 � ��80.54°<br />

E 120 V �0°<br />

b. Is ������ � 19.74 A �80.54°<br />

ZT 6.08 � ��80.54°<br />

c. Referring to Fig. 16.2, we find that V R and V C can be found by a<br />

direct application of Ohm’s law:<br />

VR � IsZ1 � (19.74 A �80.54°)(1 � �0°) � 19.74 V �80.54°<br />

VC � IsZ2 � (19.74 A �80.54°)(6 � ��90°)<br />

� 118.44 V ��9.46°<br />

d. Now that V C is known, the current I C can also be found using Ohm’s<br />

law.<br />

IC � � �59.22 A �80.54°<br />

e. Pdel � I 2 sR � (19.74 A) 2 VC 118.44 V ��9.46°<br />

� ���<br />

ZC 2 � ��90°<br />

(1 �) � 389.67 W<br />

f. Fp � cos v � cos 80.54° � 0.164 leading<br />

The fact that the total impedance has a negative phase angle (revealing<br />

that Is leads E) is a clear indication that the network is capacitive in<br />

nature and therefore has a leading power factor. The fact that the network<br />

is capacitive can be determined from the original network by first<br />

realizing that, for the parallel L-C elements, the smaller impedance predominates<br />

and results in an R-C network.<br />

EXAMPLE 16.2 For the network of Fig. 16.3:<br />

a. If I is 50 A �30°, calculate I 1 using the current divider rule.<br />

b. Repeat part (a) for I 2.<br />

c. Verify Kirchhoff’s current law at one node.<br />

Solutions:<br />

a. Redrawing the circuit as in Fig. 16.4, we have<br />

Z1 � R � j XL � 3 ��j 4 ��5 � �53.13°<br />

Z2 ��j XC ��j 8 ��8 � ��90°<br />

Using the current divider rule yields<br />

Z2I (8 � ��90°)(50 A �30°) 400 ��60°<br />

I1 ������ ���<br />

Z2 � Z1 (�j 8 �) � (3 ��j 4 �) 3 � j 4<br />

400 ��60°<br />

��� �80 A ��6.87°<br />

5 ��53.13°<br />

I<br />

ILLUSTRATIVE EXAMPLES ⏐⏐⏐ 711<br />

I<br />

I1 R 3 �<br />

X L<br />

4 �<br />

FIG. 16.3<br />

Example 16.2.<br />

I 1<br />

Z 1<br />

I 2<br />

X C<br />

I 2<br />

Z 2<br />

8 �<br />

FIG. 16.4<br />

Network of Fig. 16.3 after assigning the block<br />

impedances.

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