FR60 MB91460E Series - Microcontrollers - Fujitsu

MB91460E Series
3.3. Address mapping from CPU to parallel programming mode
The following tables show the calculation from CPU addresses to flash macro addresses which are used in
parallel programming.
3.3.1. Address mapping MB91F467EA
CPU Address
(addr)
14:0000h
to
14:FFFFh
14:0000h
to
14:FFFFh
04:0000h
to
13:FFFFh
04:0000h
to
13:FFFFh
Note: FA result is without 20:0000h offset for parallel Flash programming .
Set offset by keeping FA[21] = 1 as described in section “Parallel Flash programming mode”.
:
Condition
addr[2]==0
addr[2]==1
addr[2]==0
addr[2]==1
Flash
sectors
SA0, SA2, SA4, SA6
(8 Kbyte)
SA1, SA3, SA5, SA7
(8 Kbyte)
SA8, SA10, SA12, SA14,
SA16, SA18, SA20, SA22
(64 Kbyte)
SA9, SA11, SA13, SA15,
SA17, SA19, SA21, SA23
(64 Kbyte)
FA (flash address) Calculation
FA := addr - addr%00:4000h + (addr%00:4000h)/2
- (addr/2)%4 + addr%4 - 05:0000h
FA := addr - addr%00:4000h + (addr%00:4000h)/2
- (addr/2)%4 + addr%4 - 05:0000h
+ 00:2000h
FA := addr - addr%02:0000 + (addr%02:0000h)/2
- (addr/2)%4 + addr%4 + 0C:0000h
FA := addr - addr%02:0000h + (addr%02:0000h)/2
- (addr/2)%4 + addr%4 + 0C:0000h
+ 01:0000h
100 DS705-00002-1v3-E