FR60 MB91460E Series - Microcontrollers - Fujitsu

• ADCS1 : Access: Half-word, Byte
[bit 15] BUSY (busy flag and stop)
MB91460E Series
15 14 13 12 11 10 9 8 Bit
BUSY INT INTE PAUS STS1 STS0 STRT reserved
0 0 0 0 0 0 0 0 Initial value
R/W R/W R/W R/W R/W R/W R/W R/W Attribute
BUSY Function
Reading
Writing
A/D converter operation indication bit. Set on activation of A/D conversion
and cleared on completion.
Writing "0" to this bit during A/D conversion forcibly terminates conversion.
Use to forcibly terminate in continuous and stop modes.
• Read-modify-write instructions read the bit as "1".
• Cleared on the completion of A/D conversion in single conversion mode.
• In continuous and stop mode, the flag is not cleared until conversion is terminated by writing "0".
• Initialized to "0" by a software reset (RST).
• Do not specify forcible termination and software activation (BUSY="0" and STRT="1") at the same time.
[bit 14] INT (End of Conversion Interrupt flag)
This bit is set when conversion data is stored in ADCR.
• If bit 5 (INTE) is "1" when this bit is set, an interrupt request is generated or, if activation of DMA is enabled,
DMA is activated.
• Only clear this bit by writing "0" when A/D conversion is halted.
• Initialized to "0" by a software reset (RST).
• If DMA is used, this bit is cleared at the end of DMA transfer.
[bit 13] INTE (End of Conversion Interrupt enable)
This bit is enables or disables the conversion completion interrupt.
INTE Function
0 Disable interrupt [Initial value]
1 Enable interrupt
• Cleared by a software reset (RST).
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