FR60 MB91460E Series - Microcontrollers - Fujitsu

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MB91460E Series 4. Shutdown Operation 4.1. Transition to shutdown state Shutdown state is a special kind of the STOP state. During Shutdown, the settings in the STCR register for Oscillation Disable (STCR.OSCD1, STCR.OSCD2), Hi-Z mode (STCR.HIZ) and Oscillation Stabilization time (STCR.OS[1:0]) are valid the same kind as in normal STOP state. At recovery from Shutdown, STCR.OS[1:0] are not cleared to maintain the oscillator stabilisation time, while STCR.OSCD1, STCR.OSCD2 and STCR.HIZ are initialized by the recovery. For transition into Shutdown, do the following: • Enable at least one recovery condition (otherwise, recovery is only possible by external INITX pin) • Enable the Shutdown mode • Switch the device to STOP mode The details are explained below. 4.1.1. Precautions Before enabling Shutdown, consider the following: • Data, which is needed after recovery from Shutdown, should be copied into the Standby RAM. • The CPU should run on Main- or Sub-Oscillation, not on PLL. The PLL should be disabled. • The Sub-Regulator can be set to 1.2V in STOP mode by setting REGSEL.SUBSEL = 0x00 • Specify the levels of external interrupt signals used for recovery in EXTLV1/2 registers • Enable the channels of external interrupt signals for recovery in EXTE register 4.1.2. Deep Shutdown Settings for maximal power saving The following settings generate Shutdown without any activity on the device: • Disable all pin pull-up/pull-down settings which are not required, or set the STCR.HIZ 1 bit when going to STOP. • Set external bus pins to port mode / input direction (otherwise some pins will output constant values, see “I/O Behaviour in Shutdown” on page 91). • Don’t set Hardware Watchdog Run in STOP mode (HWWDE.STP_RUN 2 =0, this is default setting) • Disable the RC oscillator in STOP mode (CSVCR.RCE=0) • Disable the Low Voltage Detection in STOP mode (LVDET.LVEPD=1, LVDET.LVIPD=1) • Disable the Main and the Sub oscillators in STOP mode (STCR.OSCD1=1, STCR.OSCD2=1) • Set the Shutdown Enable bit SHDE.SDENB=1 to enable shutdown mode • Go to STOP: set the STOP request STCR.STOP=1 and read back STCR two times. 1. With STCR.HIZ=1, all pull-ups and pull-downs are disabled in STOP/Shutdown. 2. STP_RUN is bit [4] of HWWDE register. It enables running the Hardware Watchdog in STOP mode. STP_RUN can only be set by software, but not cleared. STP_RUN is cleared by INIT. 84 DS705-00002-1v3-E
4.1.3. Shutdown with Real Time Clock running MB91460E Series The following settings generate Shutdown with the RTC running on Main-Oscillation, Sub-Oscillation or RC clock, and with recovery by RTC enabled: • Set the RTC prescaler values depending on the clock speed (WTBR register) • If recovery by the RTC is needed: - Enable at least one of the the RTC interrupts (half-second, second, minute, hour or day) in WTCR and/or WTCE register - Enable RTC recovery: set SHDINT.RTCE=1 • If RTC uses Main Oscillation: - Disable the RC oscillator in STOP mode (CSVCR.RCE=0) - Disable the Sub oscillator in STOP mode (STCR.OSCD2=1) and keep Main oscillator running (OSCD1=0) - The RTC is connected to Main oscillation by default. • If RTC uses Sub Oscillation: - Disable the RC oscillator in STOP mode (CSVCR.RCE=0) - Disable the Main oscillator in STOP mode (STCR.OSCD1=1) and keep Sub oscillator running (OSCD2=0) - Connect the RTC to Sub oscillator: set CSCFG.CSC[1:0]=01 • If RTC uses RC clock: - Enable the RC oscillator in STOP mode (CSVCR.RCE=1, this is default setting) - Disable the Main and the Sub oscillators in STOP mode (STCR.OSCD1=1, STCR.OSCD2=1) - Connect the RTC to RC oscillator: set CSCFG.CSC[1:0]=10 • Set the Shutdown Enable bit SHDE.SDENB=1 to enable shutdown mode • Go to STOP: set the STOP request STCR.STOP=1 and read back STCR two times. 4.1.4. Hardware Watchdog in Shutdown The Hardware Watchdog can run in STOP mode, if the bit HWWDE.STP_RUN 1 is set. • Outside STOP mode, the Hardware Watchdog timeout will send an INIT signal to the CPU via the Shutdown control. • In STOP mode without Shutdown, the Hardware Watchdog timeout will send an INIT signal to the CPU via the (inactive) Shutdown control, which cancelles the STOP mode immediately. • In STOP mode with Shutdown enabled, the Hardware Watchdog timeout will set the SHDINT.HWWDF flag, causing a recovery from Shutdown. The Hardware Watchdog can be enabled in Shutdown state like follows: • Enable the Hardware Watchdog operation in STOP mode: set HWWDE.STP_RUN = 1 In parallel, this enables the RC oscillator by hardware, and the Hardware Watchdog recovery Enable bit SHDINT.HWWDE is set by hardware too. • If RTC is needed, enable it like described in 4.1.3. Shutdown with Real Time Clock running above. • Specify the levels of external interrupt signals used for recovery in EXTLV1/2 registers • Enable the channels of external interrupt signals for recovery in EXTE register • Set the Shutdown Enable bit SHDE.SDENB=1 to enable shutdown mode • Clear/restart the Hardware Watchdog: write 0 to bit HWWD.CL • Go to STOP: set the STOP request STCR.STOP=1 and read back STCR two times. 1. STP_RUN is bit [4] of HWWDE register. It enables running the Hardware Watchdog in STOP mode. STP_RUN can only be set by software, but not cleared. STP_RUN is cleared by INIT. DS705-00002-1v3-E 85
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FUJITSU SEMICONDUCTOR DATA SHEET 32
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MB91460E Series (Continued) • Rea
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MB91460E Series Sound Generator 1 c
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MB91460E Series DS705-00002-1v3-E 7
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(Continued) Pin no. Pin name I/O 66
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Page 13 and 14:
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2. Power supply/Ground pins MB91460
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Type Circuit Remarks MB91460E Serie
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Type Circuit Remarks G Mask ROM and
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Type Circuit Remarks M CMOS level t
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(Continued) Example of using opposi
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■ NOTES ON DEBUGGER 1. Execution
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■ A/D CONVERTER / RANGE COMPARATO
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3. Block Diagram of A/D Converter T
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1. On MB91F467E, ADC1 does not exis
Page 33 and 34: • ADCS1 : Access: Half-word, Byte
Page 35 and 36: MB91460E Series [bit 9] STRT (Start
Page 37 and 38: 4.2. Common Data Register (ADCR1, A
Page 39 and 40: 4.5. A/D Channel Setting Register (
Page 41 and 42: 5.2. Range Comparator Registers The
Page 43 and 44: 5.2.3. Inverted Range Selection reg
Page 45 and 46: MB91460E Series The interrupt condi
Page 47 and 48: 6. Operation of A/D Converter MB914
Page 49 and 50: 6.5. Scan Conversion The following
Page 51 and 52: MB91460E Series The automatic inter
Page 53 and 54: ■ CLOCK SUPERVISOR (New Feature)
Page 55 and 56: 2.1. Clock Supervisor Control Regis
Page 57 and 58: 3. Block Diagram Clock Supervisor M
Page 59 and 60: MB91460E Series Figure 0-4 Timing D
Page 65 and 66: 4.3. Re-enabling the RC-oscillator
Page 67 and 68: MB91460E Series Figure 0-11 Timing
Page 69 and 70: Timing Diagram: Waking up from Sub
Page 71 and 72: 4.9. RTC mode (STOP mode with Real
Page 73 and 74: 4.11. Check if reset was asserted b
Page 75 and 76: ■ MB91460E Series DS705-00002-1v3
Page 77 and 78: 2. Standby RAM MB91460E Series MB91
Page 79 and 80: 3.3. EXTE: Shutdown recovery extern
Page 81 and 82: [bit 1] RTCF: Real Time Clock recov
Page 83: 3.6. EXTLV1/2: Shutdown recovery ex
Page 87 and 88: 4.1.8. External Interrupts: Level o
Page 89 and 90: 4.3. Determining the Reset Source a
Page 91 and 92: 4.5. I/O Behaviour in Shutdown Duri
Page 93 and 94: 3. Programming model 3.1. Basic pro
Page 95 and 96: 4.3. CCR (Condition Code Register)
Page 97 and 98: ■ EMBEDDED PROGRAM/DATA MEMORY (F
Page 99 and 100: 3.2. Flash access timing settings i
Page 101 and 102: 4. Parallel Flash programming mode
Page 103 and 104: 5. Poweron Sequence in parallel pro
Page 105 and 106: 6.3. Security Vector FSV2 MB91460E
Page 107 and 108: ■ MEMORY MAPS 1. MB91F467EA 00000
Page 109 and 110: Address 000000H 000004H 000008H Reg
Page 111 and 112: (Continued) Address 0000A0H Registe
Page 113 and 114: (Continued) Address 000180H Reserve
Page 115 and 116: (Continued) Address 000200H 000204H
Page 117 and 118: (Continued) Address 000348H 00034CH
Page 119 and 120: (Continued) Address 00048CH 000490H
Page 121 and 122: (Continued) Address + 0 + 1 Registe
Page 123 and 124: Address 000704H 000708H 00070CH 000
Page 125 and 126: (Continued) Address 000D80H 000D84H
Page 127 and 128: (Continued) Address 000E80H 000E84H
Page 129 and 130: (Continued) Address 002000H to 006F
Page 131 and 132: (Continued) Address 00C080H 00C084H
Page 133 and 134: (Continued) Address 00C1A0H 00C1A4H
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Address 00F09CH 00F0A0H 00F0A4H 00F
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32bit read/write dat[31:0] dat[31:0
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(Continued) Interrupt Decimal Inter
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(Continued) Interrupt Decimal Inter
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■ RECOMMENDED SETTINGS 1. PLL and
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MB91460E Series (Continued) Modulat
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MB91460E Series (Continued) Modulat
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(Continued) Modulation Degree (k) R
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“H” level average output curren
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2. Recommended operating conditions
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3. DC characteristics MB91460E Seri
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Parameter Symbol Analog inputleakag
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MB91460E Series 4. A/D converter ch
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Digital output 3FFH 3FEH 3FDH 004H
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5. Alarm comparator characteristics
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7. AC characteristics 7.1. Clock ti
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7.3. LIN-USART Timings at VDD5 = 3.
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7.4. I 2 C AC Timings at VDD5 = 3.0
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7.5. Free-run timer clock Input pul
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MCLKO CSXn delayed CSXn ASX ADDRESS
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MCLKO MCLKI CSXn WRXn (as byte enab
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MB91460E Series 7.7.4. Synchronous
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MB91460E Series 7.7.6. Asynchronous
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7.7.8. RDY waitcycle insertion Para
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7.7.10. Clock relationships MB91460
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MCLKO DACKX DEOP delayed DACKX dela
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MCLKO CSXn delayed CSXn ASX ADDRESS
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MCLKO MCLKI CSXn WRXn (as byte enab
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MB91460E Series 7.8.4. Synchronous
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MB91460E Series 7.8.6. Asynchronous
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7.8.8. RDY waitcycle insertion Para
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7.8.10. Clock relationships MCLKO
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MCLKO DACKX DEOP delayed DACKX dela
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■ PACKAGE DIMENSION 208-pin plast
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Version/ Date Ver. 0.8 2009-10-19 V
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■ CHANGES IN THIS EDITION DS705-0
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MEMO MB91460E Series DS705-00002-1v
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MB91460E Series DS705-00002-1v3-E 2
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FR60 MB91460E Series - Microcontrollers - Fujitsu

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