FR60 MB91460E Series - Microcontrollers - Fujitsu

MB91460E Series
3.4. SHDINT: Shutdown recovery internal interrupt control and status register
The SHDINT register containes control bits and flags for enabling and indicating internal interrupts for recovery
from shutdown mode.
• SHDINT : Address 0004DBH Access: Byte
7 6 5 4 3 2 1 0
- - - - HWWDF HWWDE RTCF RTCE
X X X X 0 0 0 0 Initial value 1
X X X X retain 0 retain 0 Initial value 2
X X X X retain 0 retain retain Initial value 3
- - - -
1. Initial value after external pin INITX=0
2. Initial value after Shutdown Recovery
3. Initial value after Software Reset (RST)
[bit 7 to bit 4] Reserved bits
• The read value is undefined.
• Always write 0 to these bits.
R(RM1)/
W0
[bit 3] HWWDF: Hardware Watchdog recovery flag
HWWDF Function
1 Recovery factor from Hardware Watchdog found
0 No recovery factor from Hardware Watchdog found
• This bit is set in Shutdown mode, if HWWDE is set and if an INITX signal from Hardware Watchdog is detected.
• Writing "1" to this bit does not affect the operation.
• Writing "0" cleares the bit, external pin INITX=0 cleares the bit.
• "1" is read by a read-modify-write instruction.
[bit 2] HWWDE: Hardware Watchdog recovery enable (mirror of HWWDE.STP_RUN 1 )
HWWDE Function
1
0
Recovery reset from Hardware Watchdog is enabled,
RC clock is enabled in STOP/Shutdown mode by hardware
• This bit is a read-only mirror of HWWDE.STP_RUN, which can be set only once after reset and cannot be
cleared by CPU access.
• This bit is cleared by Software Reset (RST). Note that external pin INITX=0 or Shutdown recovery are always
followed by a Software Reset RST.
1. STP_RUN is bit HWWDE[4]
80 DS705-00002-1v3-E
R
R(RM1)/
W0
Recovery reset from Hardware Watchdog is disabled,
RC clock depends on CSVCR.RCE setting in STOP/Shutdown mode
R/W Attribute