FR60 MB91460E Series - Microcontrollers - Fujitsu

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MB91460E Series 5. Range Comparator 5.1. Range Comparator Structure The Range Comparator has 4 comparsion groups with an upper and a lower threshold register each. The 32 ADC channels can be enabled for range comparision and assigned to one of the 4 comparators individually. If enabled, the comparsision will set up to 2 flags for this ADC channel: • An interrupt flag RCOINT, signalling that the ADC result is outside the range or, by “inverted” configuration, inside the range. • An overflow flag RCOOF, showing that the range violation was an overflow and no underflow. Furthermore, each ADC channel can be enabled to send an interrupt request to the CPU, if the RCOINT flag is set. A/D Conversion result SAR[9:2] Upper/lower threshold regs Comparators RCOH0[7:0] RCOL0[7:0] RCOH1[7:0] RCOL1[7:0] RCOH2[7:0] RCOL2[7:0] RCOH3[7:0] RCOL3[7:0] AS[4:0] A/D Conversion current channel number A/D Conversion result register load pulse (strobe) ADE[31:0] A/D Channel Enable A/D Channel Control registers (per ADC channel) ADCC0 : RCOIE, RCOE, RCOS[1:0] ADCC1 : RCOIE, RCOE, RCOS[1:0] ADCC2 : RCOIE, RCOE, RCOS[1:0] ADCC3 : RCOIE, RCOE, RCOS[1:0] ... ADCC30 : RCOIE, RCOE, RCOS[1:0] ADCC31 : RCOIE, RCOE, RCOS[1:0] RCOS[1:0]: Select one of the 4 comparators for this channel RCOE : Enable Comparision for this ADC channel RCOIE: Enable Comparision Interrupt for this ADC channel > < > < > < > < Flag setting logic RCOOF [0:31] 32 Overflow flags RCOINT [0:31] 32 Interrupt flags 40 DS705-00002-1v3-E AND RCOIE[0:31] OR RCOIRS[0:31] to R-Bus to R-Bus RCOIRQ Inverted Range Selection register: Set the flags, if the ADC result is inside upper and lower threshold, instead of outside upper or lower threshold (default).
5.2. Range Comparator Registers The Range Comparator (RCO) has the following registers: • RCOHx[7:0] : Upper threshold register, one register per comparator block (x = 0...3) • RCOLx[7:0] : Lower threshold register, one register per comparator block (x = 0...3) • ADCCm[7:0] : ADC channel control, one register per 2 ADC channels (m = 0...15) • RCOIRS[0:31] : RCO Inverted Range Selection, one bit per ADC channel • RCOOF[0:31] : RCO Overflow Flags, one bit per ADC channel, read-only • RCOINT[0:31] : RCO Interrupt Flags, one bit per ADC channel 5.2.1. Range Comparator Threshold registers (RCOH0/L0 to RCOH3/L3) • RCOH0-3 : Higher threshold, access: Word, Half-word, Byte MB91460E Series 15 14 13 12 11 10 9 8 Bit RCOH7 RCOH6 RCOH5 RCOH4 RCOH3 RCOH2 RCOH1 RCOH0 1 1 1 1 1 1 1 1 Initial value R/W R/W R/W R/W R/W R/W R/W R/W Attribute [bit 7:0] RCOH[7:0] (Range Comparator High threshold) The RCOH bits define the higher comparision threshold of the Range Comparator channel. The upper Range Comparator compares that the upper 8 bits of the ADC conversion result are higher then RCOH[7:0] • RCOL0-3 : Lower threshold, access: Word, Half-word, Byte 7 6 5 4 3 2 1 0 Bit RCOL7 RCOL6 RCOL5 RCOL4 RCOL3 RCOL2 RCOL1 RCOL0 0 0 0 0 0 0 0 0 Initial value R/W R/W R/W R/W R/W R/W R/W R/W Attribute [bit 7:0] RCOL[7:0] (Range Comparator Low threshold) The RCOL bits define the lower comparision threshold of the Range Comparator channel. The lower Range Comparator compares that the upper 8 bits of the ADC conversion result are lower then RCOL[7:0] DS705-00002-1v3-E 41
Page 1 and 2: FUJITSU SEMICONDUCTOR DATA SHEET 32
Page 3 and 4: MB91460E Series (Continued) • Rea
Page 5 and 6: MB91460E Series Sound Generator 1 c
Page 7 and 8: MB91460E Series DS705-00002-1v3-E 7
Page 9 and 10: (Continued) Pin no. Pin name I/O 66
Page 15 and 16: 2. Power supply/Ground pins MB91460
Page 17 and 18: Type Circuit Remarks MB91460E Serie
Page 19 and 20: Type Circuit Remarks G Mask ROM and
Page 21 and 22: Type Circuit Remarks M CMOS level t
Page 23 and 24: (Continued) Example of using opposi
Page 25 and 26: ■ NOTES ON DEBUGGER 1. Execution
Page 27 and 28: ■ A/D CONVERTER / RANGE COMPARATO
Page 29 and 30: 3. Block Diagram of A/D Converter T
Page 31 and 32: 1. On MB91F467E, ADC1 does not exis
Page 33 and 34: • ADCS1 : Access: Half-word, Byte
Page 35 and 36: MB91460E Series [bit 9] STRT (Start
Page 37 and 38: 4.2. Common Data Register (ADCR1, A
Page 39: 4.5. A/D Channel Setting Register (
Page 43 and 44: 5.2.3. Inverted Range Selection reg
Page 45 and 46: MB91460E Series The interrupt condi
Page 47 and 48: 6. Operation of A/D Converter MB914
Page 49 and 50: 6.5. Scan Conversion The following
Page 51 and 52: MB91460E Series The automatic inter
Page 53 and 54: ■ CLOCK SUPERVISOR (New Feature)
Page 55 and 56: 2.1. Clock Supervisor Control Regis
Page 57 and 58: 3. Block Diagram Clock Supervisor M
Page 59 and 60: MB91460E Series Figure 0-4 Timing D
Page 65 and 66: 4.3. Re-enabling the RC-oscillator
Page 67 and 68: MB91460E Series Figure 0-11 Timing
Page 69 and 70: Timing Diagram: Waking up from Sub
Page 71 and 72: 4.9. RTC mode (STOP mode with Real
Page 73 and 74: 4.11. Check if reset was asserted b
Page 75 and 76: ■ MB91460E Series DS705-00002-1v3
Page 77 and 78: 2. Standby RAM MB91460E Series MB91
Page 79 and 80: 3.3. EXTE: Shutdown recovery extern
Page 81 and 82: [bit 1] RTCF: Real Time Clock recov
Page 83 and 84: 3.6. EXTLV1/2: Shutdown recovery ex
Page 85 and 86: 4.1.3. Shutdown with Real Time Cloc
Page 87 and 88: 4.1.8. External Interrupts: Level o
Page 89 and 90: 4.3. Determining the Reset Source a
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4.5. I/O Behaviour in Shutdown Duri
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3. Programming model 3.1. Basic pro
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4.3. CCR (Condition Code Register)
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■ EMBEDDED PROGRAM/DATA MEMORY (F
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3.2. Flash access timing settings i
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4. Parallel Flash programming mode
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5. Poweron Sequence in parallel pro
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6.3. Security Vector FSV2 MB91460E
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■ MEMORY MAPS 1. MB91F467EA 00000
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Address 000000H 000004H 000008H Reg
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(Continued) Address 0000A0H Registe
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(Continued) Address 000180H Reserve
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(Continued) Address 000200H 000204H
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(Continued) Address 000348H 00034CH
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(Continued) Address 00048CH 000490H
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(Continued) Address + 0 + 1 Registe
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Address 000704H 000708H 00070CH 000
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(Continued) Address 000D80H 000D84H
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(Continued) Address 000E80H 000E84H
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(Continued) Address 002000H to 006F
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(Continued) Address 00C080H 00C084H
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(Continued) Address 00C1A0H 00C1A4H
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Address 00F09CH 00F0A0H 00F0A4H 00F
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32bit read/write dat[31:0] dat[31:0
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(Continued) Interrupt Decimal Inter
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(Continued) Interrupt Decimal Inter
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■ RECOMMENDED SETTINGS 1. PLL and
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MB91460E Series (Continued) Modulat
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MB91460E Series (Continued) Modulat
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(Continued) Modulation Degree (k) R
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“H” level average output curren
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2. Recommended operating conditions
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3. DC characteristics MB91460E Seri
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Parameter Symbol Analog inputleakag
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MB91460E Series 4. A/D converter ch
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Digital output 3FFH 3FEH 3FDH 004H
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5. Alarm comparator characteristics
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7. AC characteristics 7.1. Clock ti
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7.3. LIN-USART Timings at VDD5 = 3.
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7.4. I 2 C AC Timings at VDD5 = 3.0
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7.5. Free-run timer clock Input pul
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MCLKO CSXn delayed CSXn ASX ADDRESS
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MCLKO MCLKI CSXn WRXn (as byte enab
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MB91460E Series 7.7.4. Synchronous
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MB91460E Series 7.7.6. Asynchronous
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7.7.8. RDY waitcycle insertion Para
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7.7.10. Clock relationships MB91460
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MCLKO DACKX DEOP delayed DACKX dela
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MCLKO CSXn delayed CSXn ASX ADDRESS
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MCLKO MCLKI CSXn WRXn (as byte enab
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MB91460E Series 7.8.4. Synchronous
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MB91460E Series 7.8.6. Asynchronous
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7.8.8. RDY waitcycle insertion Para
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7.8.10. Clock relationships MCLKO
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MCLKO DACKX DEOP delayed DACKX dela
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■ PACKAGE DIMENSION 208-pin plast
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Version/ Date Ver. 0.8 2009-10-19 V
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■ CHANGES IN THIS EDITION DS705-0
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MEMO MB91460E Series DS705-00002-1v
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MB91460E Series DS705-00002-1v3-E 2
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FR60 MB91460E Series - Microcontrollers - Fujitsu

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