FR60 MB91460E Series - Microcontrollers - Fujitsu

More documents

Recommendations

Info

MB91460E Series ■ REVISION HISTORY Version/ Date Ver. 0.01 2009-04-16 Ver. 0.2 2009-07-03 Ver. 0.3 2009-08-03 Ver. 0.4 2009-08-04 Ver. 0.5 2009-08-19 Ver. 0.6 2009-09-08 Page Section Change Results - - Initial version based on MB91F467D all all Various updates following the proof read results on other MB91460 series datasheets 76 Shutdown Mode Chapter “Shutdown Mode” added 4 Product Lineup Corrected that the software watchdog cannot be activated in SLEEP/STOP 76- 92 Chapter Shutdown Mode Total update 120 IO Map; SHDINT register Removed bits [3:2] 151 ELECTRICAL CHARACTERISTICS, Absolute maximum ratings Permitted power dissipation (calculated) added 157 DC Characteristics Added Sum input leakage current 159 A/D converter characteristics; Zero reading voltage, Full scale reading voltage Changed the units from “LSB” into “V” and the values from + into + 165 AC Characteristics Removed the AC specification temporary 201 Package Dimension Updated the the drawing of FPT-208P-M04 into FPT-208P-M06, updated the URL for download all Total update after first spec review No change bars in this revision! 73 USART LIN/FIFO (Extension) This chapter added for “End of Transmission” IRQ 108 I/O Map Marked all differences versus MB91F467D with colors 138 Interrupt Vector Table Added the USART “End of Transmission” IRQs 87 86 Shutdown mode: External Interrupts: Level or Edge Setting Shutdown mode: Input Voltage Selection 80 Shutdown mode: SHDINT register 78 Shutdown mode: All registers 89 Shutdown mode: Determining the reset source Added this section Added this section Re-added bits [3:2] HWWDF, HWWDE for hardware watchdog Updated the bit descriptions of all flags, updated the reset conditions of all registers Figure updated, Hardware watchdog + Clock supervisor updated 85 Shutdown mode: Hardware watchdog Updated the parts about Hardware watchdog, Clock Supervisor completely 86 Shutdown mode: Clock Supervisor 202 DS705-00002-1v3-E
Version/ Date Ver. 0.8 2009-10-19 Ver. 0.9 2009-11-24 Ver. 1.0 2009-12-15 Ver. 1.1 2010-01-21 Ver 1.11 2010-06-02 MB91460E Series Page Section Change Results 77 Shutdwon Mode: Standby RAM Changed: 1 wait cycle for read, 0 wait cycles for write 78 Hardware Watchdog: Caution 84 Shutdown Mode: Precautions 90 Shutdown Mode: Registers which are not initialized by Shutdown Recovery 26 Block Diagram 56 Clock Supervisor, CSVCR register Updated “Difference between watchdog reset, external reset and Power-on reset” Add setting of EXTE and EXTLV; removed this from Deep Shutdown settings Added this section Corrected the connection of Standby RAM (to extended D-bus) Added note that bit SCKS must not be changed during CPU runs in Sub clock. all Header Changed from “Preliminary Short Specification” into “Preliminary Datasheet” 3 Features Removed the note about PHILIPS I2C license 15 Pin Description : Power supply/Ground pins Added pin 208 to the list of VDD35 pins 77 Shutdown Mode: Standby RAM StandBy RAM 1 wait state for read and write 125 I/O Map Added note about external bus PFR initial values 137 I/O Map StandBy RAM 1 wait state for read and write 138 Interrupt Vector Table Re-arranged the table to set correct page breaks 201 Package Dimension Link to package database corrected 74 USART LIN/FIFO (Extension) : FIFO status register for End of Transmission interrupt control Bits [12:8] of FSR register named NVFD[5:0] (Number of valid FIFO data), name is needed for Softune header file. 77 Shutdown Mode: Standby RAM Added notes that, if CLKP is slower then CLKB, 78 Shutdown Mode: SHDE Register there must be a wait time between setting RAMEN and Standby RAM access. 76 Shutdown Mode: Overview 88 Shutdown Mode: Recovery Added notes that reset by external pin INITX=0 will kill the Shutdown state and restart the device like at 90 Shutdown Mode: Registers which are not initialized by Shutdown Recovery power-on. 4 Product Lineup Changed max. CLKB frequency to 100 MHz 143 144 158 165 Recommended Settings PLL and Clockgear settings Enabled / allowed the settings which reach Recommended Settings Clock modulator settings Electrical Characteristics DC Characteristics Electrical Characteristics AC Characteristics CLKB up to 100MHz Changed Icc max for CLKB:P:T:CAN = 100:50:50:50 MHz; Updated all current consumption characteristics Chapter AC Characteristics added DS705-00002-1v3-E 203
Page 1 and 2:
FUJITSU SEMICONDUCTOR DATA SHEET 32
Page 3 and 4:
MB91460E Series (Continued) • Rea
Page 5 and 6:
MB91460E Series Sound Generator 1 c
Page 7 and 8:
MB91460E Series DS705-00002-1v3-E 7
Page 9 and 10:
(Continued) Pin no. Pin name I/O 66
Page 11 and 12:
Page 13 and 14:
Page 15 and 16:
2. Power supply/Ground pins MB91460
Page 17 and 18:
Type Circuit Remarks MB91460E Serie
Page 19 and 20:
Type Circuit Remarks G Mask ROM and
Page 21 and 22:
Type Circuit Remarks M CMOS level t
Page 23 and 24:
(Continued) Example of using opposi
Page 25 and 26:
■ NOTES ON DEBUGGER 1. Execution
Page 27 and 28:
■ A/D CONVERTER / RANGE COMPARATO
Page 29 and 30:
3. Block Diagram of A/D Converter T
Page 31 and 32:
1. On MB91F467E, ADC1 does not exis
Page 33 and 34:
• ADCS1 : Access: Half-word, Byte
Page 35 and 36:
MB91460E Series [bit 9] STRT (Start
Page 37 and 38:
4.2. Common Data Register (ADCR1, A
Page 39 and 40:
4.5. A/D Channel Setting Register (
Page 41 and 42:
5.2. Range Comparator Registers The
Page 43 and 44:
5.2.3. Inverted Range Selection reg
Page 45 and 46:
MB91460E Series The interrupt condi
Page 47 and 48:
6. Operation of A/D Converter MB914
Page 49 and 50:
6.5. Scan Conversion The following
Page 51 and 52:
MB91460E Series The automatic inter
Page 53 and 54:
■ CLOCK SUPERVISOR (New Feature)
Page 55 and 56:
2.1. Clock Supervisor Control Regis
Page 57 and 58:
3. Block Diagram Clock Supervisor M
Page 59 and 60:
MB91460E Series Figure 0-4 Timing D
Page 61 and 62:
Page 63 and 64:
Page 65 and 66:
4.3. Re-enabling the RC-oscillator
Page 67 and 68:
MB91460E Series Figure 0-11 Timing
Page 69 and 70:
Timing Diagram: Waking up from Sub
Page 71 and 72:
4.9. RTC mode (STOP mode with Real
Page 73 and 74:
4.11. Check if reset was asserted b
Page 75 and 76:
■ MB91460E Series DS705-00002-1v3
Page 77 and 78:
2. Standby RAM MB91460E Series MB91
Page 79 and 80:
3.3. EXTE: Shutdown recovery extern
Page 81 and 82:
[bit 1] RTCF: Real Time Clock recov
Page 83 and 84:
3.6. EXTLV1/2: Shutdown recovery ex
Page 85 and 86:
4.1.3. Shutdown with Real Time Cloc
Page 87 and 88:
4.1.8. External Interrupts: Level o
Page 89 and 90:
4.3. Determining the Reset Source a
Page 91 and 92:
4.5. I/O Behaviour in Shutdown Duri
Page 93 and 94:
3. Programming model 3.1. Basic pro
Page 95 and 96:
4.3. CCR (Condition Code Register)
Page 97 and 98:
■ EMBEDDED PROGRAM/DATA MEMORY (F
Page 99 and 100:
3.2. Flash access timing settings i
Page 101 and 102:
4. Parallel Flash programming mode
Page 103 and 104:
5. Poweron Sequence in parallel pro
Page 105 and 106:
6.3. Security Vector FSV2 MB91460E
Page 107 and 108:
■ MEMORY MAPS 1. MB91F467EA 00000
Page 109 and 110:
Address 000000H 000004H 000008H Reg
Page 111 and 112:
(Continued) Address 0000A0H Registe
Page 113 and 114:
(Continued) Address 000180H Reserve
Page 115 and 116:
(Continued) Address 000200H 000204H
Page 117 and 118:
(Continued) Address 000348H 00034CH
Page 119 and 120:
(Continued) Address 00048CH 000490H
Page 121 and 122:
(Continued) Address + 0 + 1 Registe
Page 123 and 124:
Address 000704H 000708H 00070CH 000
Page 125 and 126:
(Continued) Address 000D80H 000D84H
Page 127 and 128:
(Continued) Address 000E80H 000E84H
Page 129 and 130:
(Continued) Address 002000H to 006F
Page 131 and 132:
(Continued) Address 00C080H 00C084H
Page 133 and 134:
(Continued) Address 00C1A0H 00C1A4H
Page 135 and 136:
Address 00F09CH 00F0A0H 00F0A4H 00F
Page 137 and 138:
32bit read/write dat[31:0] dat[31:0
Page 139 and 140:
(Continued) Interrupt Decimal Inter
Page 141 and 142:
(Continued) Interrupt Decimal Inter
Page 143 and 144:
■ RECOMMENDED SETTINGS 1. PLL and
Page 145 and 146:
MB91460E Series (Continued) Modulat
Page 147 and 148:
MB91460E Series (Continued) Modulat
Page 149 and 150:
(Continued) Modulation Degree (k) R
Page 151 and 152: “H” level average output curren
Page 153 and 154: 2. Recommended operating conditions
Page 155 and 156: 3. DC characteristics MB91460E Seri
Page 157 and 158: Parameter Symbol Analog inputleakag
Page 159 and 160: MB91460E Series 4. A/D converter ch
Page 161 and 162: Digital output 3FFH 3FEH 3FDH 004H
Page 163 and 164: 5. Alarm comparator characteristics
Page 165 and 166: 7. AC characteristics 7.1. Clock ti
Page 167 and 168: 7.3. LIN-USART Timings at VDD5 = 3.
Page 169 and 170: 7.4. I 2 C AC Timings at VDD5 = 3.0
Page 171 and 172: 7.5. Free-run timer clock Input pul
Page 173 and 174: MCLKO CSXn delayed CSXn ASX ADDRESS
Page 175 and 176: MCLKO MCLKI CSXn WRXn (as byte enab
Page 177 and 178: MB91460E Series 7.7.4. Synchronous
Page 179 and 180: MB91460E Series 7.7.6. Asynchronous
Page 181 and 182: 7.7.8. RDY waitcycle insertion Para
Page 183 and 184: 7.7.10. Clock relationships MB91460
Page 185 and 186: MCLKO DACKX DEOP delayed DACKX dela
Page 187 and 188: MCLKO CSXn delayed CSXn ASX ADDRESS
Page 189 and 190: MCLKO MCLKI CSXn WRXn (as byte enab
Page 191 and 192: MB91460E Series 7.8.4. Synchronous
Page 193 and 194: MB91460E Series 7.8.6. Asynchronous
Page 195 and 196: 7.8.8. RDY waitcycle insertion Para
Page 197 and 198: 7.8.10. Clock relationships MCLKO
Page 199 and 200: MCLKO DACKX DEOP delayed DACKX dela
Page 201: ■ PACKAGE DIMENSION 208-pin plast
Page 205 and 206: ■ CHANGES IN THIS EDITION DS705-0
Page 207 and 208: MEMO MB91460E Series DS705-00002-1v
Page 209: MB91460E Series DS705-00002-1v3-E 2
show all

FR60 MB91460E Series - Microcontrollers - Fujitsu

Create successful ePaper yourself

Delete template?

Save as template?